PIC18F66J60-I/PT Microchip Technology, PIC18F66J60-I/PT Datasheet - Page 219
![IC PIC MCU FLASH 32KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F66J60-I/PT
Manufacturer Part Number
PIC18F66J60-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F66J65-IPT.pdf
(8 pages)
4.PIC18F66J65-IPT.pdf
(480 pages)
5.PIC18F66J65-IPT.pdf
(4 pages)
6.PIC18F97J60-IPT.pdf
(476 pages)
Specifications of PIC18F66J60-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F66J60-I/PT
Manufacturer:
DIODES
Quantity:
31 100
Company:
Part Number:
PIC18F66J60-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F97J60-IPT PDF datasheet #6
- Current page: 219 of 480
- Download datasheet (8Mb)
18.2.4
These SFRs are used to control the operations of the
MAC and, through the MIIM, the PHY. The MAC and
MII registers occupy data addresses E80h-E85h,
E8Ah, and EA0h through EB9h.
Although MAC and MII registers appear in the general
memory map of the microcontroller, these registers are
embedded inside the MAC module. Host interface logic
translates the microcontroller data/address bus data to
be able to access these registers. The host interface
logic imposes restrictions on how firmware is able to
access the MAC and MII SFRs. See the following
notes.
REGISTER 18-4:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
MAC AND MII REGISTERS
Unimplemented: Read as ‘0’
Reserved: Do not use
TXPAUS: Pause Control Frame Transmission Enable bit
1 = Allow the MAC to transmit pause control frames (needed for flow control in full duplex)
0 = Disallow pause frame transmissions
RXPAUS: Pause Control Frame Reception Enable bit
1 = Inhibit transmissions when pause control frames are received (normal operation)
0 = Ignore pause control frames which are received
PASSALL: Pass All Received Frames Enable bit
1 = Control frames received by the MAC will be written into the receive buffer if not filtered out
0 = Control frames will be discarded after being processed by the MAC (normal operation)
MARXEN: MAC Receive Enable bit
1 = Enable packets to be received by the MAC
0 = Disable packet reception
U-0
—
MACON1: MAC CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
U-0
—
R-0
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F97J60 FAMILY
TXPAUS
R/W-0
The three MACON registers control specific MAC oper-
ations and packet configuration operations. They are
shown in Register 18-4 through Register 18-6.
The MII registers are used to control the MIIM interface
and serve as the communication channel with the PHY
registers. They are shown in Register 18-7 and
Register 18-8.
Note 1: Do not access the MAC and MII SFRs
2: Back-to-back accesses of MAC or MII
unless the Ethernet module is enabled
(ETHEN = 1).
registers are not supported. Between any
instruction which addresses a MAC or MII
register, at least one NOP or other
instruction must be executed.
RXPAUS
R/W-0
x = Bit is unknown
PASSALL
R/W-0
DS39762E-page 219
MARXEN
R/W-0
bit 0
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