PIC18F66J60-I/PT Microchip Technology, PIC18F66J60-I/PT Datasheet - Page 469

• Manufacturer Part Number: PIC18F66J60-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RESET ............................................................................. 389
Reset .................................................................................. 53
Resets .............................................................................. 345
RETFIE ............................................................................ 390
RETLW ............................................................................ 390
RETURN .......................................................................... 391
Return Address Stack ........................................................ 71
Return Stack Pointer (STKPTR) ........................................ 72
Revision History ............................................................... 457
RLCF ................................................................................ 391
RLNCF ............................................................................. 392
© 2007 Microchip Technology Inc.
PHCON1 (PHY Control 1) ........................................ 221
PHCON2 (PHY Control 2) ........................................ 222
PHIE (PHY Interrupt Enable) ................................... 228
PHIR (PHY Interrupt Request, Flag) ........................ 228
PHLCON (PHY Module LED Control) ...................... 224
PHSTAT1 (Physical Layer Status 1) ........................ 221
PHSTAT2 (Physical Layer Status 2) ........................ 223
PIE1 (Peripheral Interrupt Enable 1) ........................ 127
PIE2 (Peripheral Interrupt Enable 2) ........................ 128
PIE3 (Peripheral Interrupt Enable 3) ........................ 129
PIR1 (Peripheral Interrupt
PIR2 (Peripheral Interrupt
PIR3 (Peripheral Interrupt
PSPCON (Parallel Slave Port Control) .................... 160
RCON (Reset Control) ....................................... 54, 133
RCSTAx (Receive Status and Control x) ................. 303
SSPxCON1 (MSSPx Control 1, I
SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 257
SSPxCON2 (MSSPx Control 2,
SSPxCON2 (MSSPx Control 2,
SSPxSTAT (MSSPx Status, I
SSPxSTAT (MSSPx Status, SPI Mode) .................. 256
STATUS ..................................................................... 87
STKPTR (Stack Pointer) ............................................ 72
T0CON (Timer0 Control) .......................................... 163
T1CON (Timer1 Control) .......................................... 167
T2CON (Timer2 Control) .......................................... 173
T3CON (Timer3 Control) .......................................... 175
T4CON (Timer4 Control) .......................................... 179
TXSTAx (Transmit Status and Control x) ................. 302
WDTCON (Watchdog Timer Control) ...................... 353
Brown-out Reset (BOR) ............................................. 53
Configuration Mismatch (CM) .................................... 53
MCLR Reset, During
MCLR Reset, Normal Operation ................................ 53
Power-on Reset (POR) .............................................. 53
Reset Instruction ........................................................ 53
Stack Full Reset ......................................................... 53
Stack Underflow Reset .............................................. 53
State of Registers ...................................................... 58
Watchdog Timer (WDT) Reset ................................... 53
Brown-out Reset (BOR) ........................................... 345
Oscillator Start-up Timer (OST) ............................... 345
Power-on Reset (POR) ............................................ 345
Power-up Timer (PWRT) ......................................... 345
Stack Full/Underflow .................................................. 73
Request (Flag) 1) ............................................. 124
Request (Flag) 2) ............................................. 125
Request (Flag) 3) ............................................. 126
I
I
Power-Managed Modes ..................................... 53
2
2
C Master Mode) ............................................ 268
C Slave Mode) .............................................. 269
2
C Mode) ................... 266
2
C Mode) .............. 267
Preliminary
PIC18F97J60 FAMILY
RRCF ............................................................................... 392
RRNCF ............................................................................ 393
S
SCKx ............................................................................... 255
SDIx ................................................................................. 255
SDOx ............................................................................... 255
SEC_IDLE Mode ............................................................... 50
SEC_RUN Mode ................................................................ 46
Serial Clock, SCKx .......................................................... 255
Serial Data In (SDIx) ........................................................ 255
Serial Data Out (SDOx) ................................................... 255
Serial Peripheral Interface. See SPI Mode.
SETF ............................................................................... 393
Slave Select (SSx) ........................................................... 255
SLEEP ............................................................................. 394
Sleep
Software Simulator (MPLAB SIM) ................................... 410
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 345
Special Function Registers
SPI Mode (MSSP)
SSPOV ............................................................................ 290
SSPOV Status Flag ......................................................... 290
SSPSTAT Register
SSPxSTAT Register
SSx .................................................................................. 255
SUBFSR .......................................................................... 405
SUBFWB ......................................................................... 394
SUBLW ............................................................................ 395
SUBULNK ........................................................................ 405
SUBWF ............................................................................ 395
SUBWFB ......................................................................... 396
SWAPF ............................................................................ 396
T
Table Pointer Operations (table) ........................................ 98
Table Reads/Table Writes ................................................. 73
TBLRD ............................................................................. 397
TBLWT ............................................................................ 398
OSC1 and OSC2 Pin States ...................................... 44
Ethernet SFRs ........................................................... 80
Associated Registers ............................................... 264
Bus Mode Compatibility ........................................... 263
Clock Speed and Module Interactions ..................... 263
Effects of a Reset .................................................... 263
Enabling SPI I/O ...................................................... 259
Master Mode ............................................................ 260
Master/Slave Connection ........................................ 259
Operation ................................................................. 258
Operation in Power-Managed Modes ...................... 263
Serial Clock ............................................................. 255
Serial Data In ........................................................... 255
Serial Data Out ........................................................ 255
Slave Mode .............................................................. 261
Slave Select ............................................................. 255
Slave Select Synchronization .................................. 261
SPI Clock ................................................................. 260
Typical Connection .................................................. 259
R/W Bit .................................................................... 272
R/W Bit .................................................................... 270
DS39762C-page 467