DSPIC30F3012-20I/ML Microchip Technology, DSPIC30F3012-20I/ML Datasheet - Page 29
DSPIC30F3012-20I/ML
Manufacturer Part Number
DSPIC30F3012-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(210 pages)
2.DSPIC30F2011-20ISO.pdf
(6 pages)
3.DSPIC30F3012-20ISO.pdf
(14 pages)
4.DSPIC30F3012-20ISO.pdf
(20 pages)
5.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F3012-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
12
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN5 - SOCKET TRANS ICE 18DIP TO 44QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301220IML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F3012-20I/ML
Manufacturer:
Microchip Technology
Quantity:
135
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F3012-20ISO PDF datasheet #3
- DSPIC30F3012-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- Current page: 29 of 210
- Download datasheet (3Mb)
3.0
3.1
The program address space is 4M instruction words.
The
dsPIC30F2011/2012/3012/3013 devices is shown in
Figure
Program memory is addressable by a 24-bit value from
either the 23-bit PC, table instruction Effective Address
(EA), or data space EA, when program space is
mapped into data space as defined by
that the program space address is incremented by two
between successive program words in order to provide
compatibility with data space addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which uses TBLPAG<7> to determine user or configu-
ration space access. In
Address Construction, bit 23 allows access to the
Device ID, the User ID and the Configuration bits.
Otherwise, bit 23 is always clear.
© 2010 Microchip Technology Inc.
Note:
program
3-1.
MEMORY ORGANIZATION
Program Address Space
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
space
memory
Table
Reference
3-1, Program Space
maps
dsPIC30F2011/2012/3012/3013
Table
3-1. Note
Manual”
for
the
DS70139G-page 29
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