PIC16C71-20/SO Microchip Technology, PIC16C71-20/SO Datasheet - Page 65

• Manufacturer Part Number: PIC16C71-20/SO
• Description: IC MCU OTP 1KX14 A/D 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C71-20/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MIL309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

8.7
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled
(Section 8.1).
8.7.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
FIGURE 8-20: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 8-21: SUMMARY OF WATCHDOG TIMER REGISTERS
Applicable Devices
Address
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 8-1, Figure 8-2 and Figure 8-3 for operation of these bits.
Note: PSA and PS2:PS0 are bits in the OPTION register.
1997 Microchip Technology Inc.
DD
Watchdog Timer (WDT)
WDT PERIOD
and process variations from part to part (see
by
Name
Config. bits
OPTION
clearing
WDT Timer
Enable Bit
710 71 711 715
WDT
configuration
RBPU
Bit 7
From TMR0 Clock Source
(Figure 6-6)
(1)
BODEN
INTEDG
bit
Bit 6
0
1
WDTE
(1)
PSA
M
U
X
T0CS
Bit 5
CP1
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT and
the postscaler, if assigned to the WDT, and prevent it
from timing out and generating a device RESET condi-
tion.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
8.7.2
It should also be taken into account that under worst
case conditions (V
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
T0SE
Bit 4
CP0
0
Note:
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
WDT PROGRAMMING CONSIDERATIONS
PWRTE
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
1
Bit 3
PSA
8
(1)
DD
PSA
To TMR0 (Figure 6-6)
= Min., Temperature = Max., and
WDTE
Bit 2
PS2
PIC16C71X
PS2:PS0
FOSC1
Bit 1
PS1
DS30272A-page 65
FOSC0
Bit 0
PS0