PIC16LF767-I/SS Microchip Technology, PIC16LF767-I/SS Datasheet - Page 235
![IC PIC MCU FLASH 8KX14 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16LF767-I/SS
Manufacturer Part Number
PIC16LF767-I/SS
Description
IC PIC MCU FLASH 8KX14 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF767-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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TABLE 18-12: I
2004 Microchip Technology Inc.
100*
101*
102*
103*
90*
91*
106*
107*
92*
109*
110*
Note 1:
Param.
No.
2:
*
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
R
HIGH
LOW
F
HD
HD
BUF
B
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I
the requirement, T
not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line, T
(according to the standard mode I
:
:
:
:
:
STA
DAT
STO
STA
DAT
2
C™ BUS DATA REQUIREMENTS
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
Start Condition
Setup Time
Start Condition Hold
Time
Data Input Hold
Time
Data Input Setup
Time
Stop Condition
Setup Time
Output Valid from
Clock
Bus Free Time
Bus Capacitive Loading
SU
:
Characteristic
DAT
2
C™ bus device can be used in a Standard mode (100 kHz) I
250 ns, must then be met. This will automatically be the case if the device does
100 kHz mode
400 kHz mode
SSP module
100 kHz mode
400 kHz mode
SSP module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
2
C bus specification), before the SCL line is released.
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
R
CY
CY
max. + T
B
B
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SU
:
DAT
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
= 1000 + 250 = 1250 ns
PIC16F7X7
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
C
10-400 pF
C
10-400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
2
Conditions
C bus system but
DS30498C-page 233
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