DSPIC30F4013-30I/ML Microchip Technology, DSPIC30F4013-30I/ML Datasheet - Page 133
DSPIC30F4013-30I/ML
Manufacturer Part Number
DSPIC30F4013-30I/ML
Description
IC DSPIC MCU/DSP 48K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3014-30IPT.pdf
(228 pages)
2.DSPIC30F3014-30IPT.pdf
(16 pages)
3.DSPIC30F3014-30IPT.pdf
(6 pages)
4.DSPIC30F3014-30IPT.pdf
(14 pages)
5.DSPIC30F3014-30IPT.pdf
(20 pages)
6.DSPIC30F3014-20IP.pdf
(226 pages)
Specifications of DSPIC30F4013-30I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
48KB
Supply Voltage Range
2.5V To 5.5V
Package
44QFN EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
30
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
13-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F401330IML
- DSPIC30F3014-30IPT PDF datasheet
- DSPIC30F3014-30IPT PDF datasheet #2
- DSPIC30F3014-30IPT PDF datasheet #3
- DSPIC30F3014-30IPT PDF datasheet #4
- DSPIC30F3014-30IPT PDF datasheet #5
- DSPIC30F3014-20IP PDF datasheet #6
- Current page: 133 of 226
- Download datasheet (4Mb)
19.4
The conversion trigger terminates acquisition and
starts the requested conversions.
The SSRC<2:0> bits select the source of the conver-
sion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit causes
the conversion trigger.
When SSRC<2:0> = 111 (Auto-Convert mode), the
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple
channels. The SAMC bits must always be at least one
clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
19.5
Clearing the ADON bit during a conversion aborts the
current conversion and stops the sampling sequencing
until the next sampling trigger. The ADCBUF is not
updated with the partially completed A/D conversion
sample. That is, the ADCBUF will continue to contain
the value of the last completed conversion (or the last
value written to the ADCBUF register).
If clearing of the ADON bit coincides with an auto-start,
the clearing has a higher priority and a new conversion
does not start.
19.6
The ADC conversion requires 14 T
the ADC conversion clock is software selected, using a
6-bit counter. There are 64 possible options for T
EQUATION 19-1:
© 2008 Microchip Technology Inc.
Programming the Start of
Conversion Trigger
Aborting a Conversion
Selecting the ADC Conversion
Clock
T
AD
= T
CY
* (0.5*(ADCS<5:0> + 1))
CLOCK
ADC CONVERSION
AD
. The source of
AD
.
The internal RC oscillator is selected by setting the
ADRC bit.
For correct ADC conversions, the ADC conversion
clock (T
time of 334 nsec (for V
“Electrical Characteristics” for minimum T
other operating conditions.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 19-1:
Since,
Sampling Time = Acquisition Time + Conversion Time
Therefore,
Sampling Rate =
If SSRC<2:0> = 111 and SAMC<4:0> = 00001
dsPIC30F3014/4013
Therefore,
Set ADCS<5:0> = 19
AD
ADCS<5:0> = 2
Minimum T
) must be selected to ensure a minimum T
Actual T
= ~200 kHz
= 1 T
= 15 x 334 nsec
AD
T
(15 x 334 nsec)
AD
CY
=
AD
= 2 •
= 19
=
= 334 nsec
DD
ADC CONVERSION
CLOCK AND SAMPLING
RATE CALCULATION
= 334 nsec
= 33.33 nsec (30 MIPS)
+ 14 T
T
33.33 nsec
= 5V). Refer to Section 23.0
1
T
T
CY
2
AD
33.33 nsec
CY
334 nsec
2
(ADCS<5:0> + 1)
AD
– 1
DS70138F-page 131
(19 + 1)
– 1
AD
under
AD
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