DSPIC33FJ128MC706-I/PT Microchip Technology, DSPIC33FJ128MC706-I/PT Datasheet - Page 5

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: IC DSPIC MCU/DSP 128K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC706-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 16 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 4096 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
ECAN
UART
PWM
PWM
PWM
PWM
PWM
PWM
ADC
QEI
QEI
QEI
SPI
SPI
I
I/O
2
C
Only those issues indicated in the last column apply to the current silicon revision.
PWM Counter
Latched Fault
Accumulation
Accumulation
Consumption
Timer Gated
Timer Gated
Sleep Mode
Generator 2
Single-Shot
Doze Mode
Generation
Generator
SILICON ISSUE SUMMARY (CONTINUED)
Idle Mode
Operation
Character
SDO1 Pin
FRMDLY
Transmit
Register
Interrupt
Feature
in Sleep
Current
Mode
Break
Mode
Mode
Slave
Mode
PWM
—
Number
Item
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
Subsequent faults in the same timer cycle are missed during a
The SDO1 pin may toggle while the device is being
The WAKIF bit in the CxINTF register cannot be cleared by
software instruction after the device has been interrupted from
Sleep by activity on the CAN bus.
After the ACKSTAT bit is set when receiving a NACK, it may be
cleared by the reception of a Start or Stop bit.
There is a glitch in the PWMxL signal in Single-Shot mode with
complementary output. Another glitch occurs when resuming
from a Fault condition in Free-Running mode with
complementary output.
latched fault.
Under certain conditions, the PWM outputs, PWM2H and
PWM2L, do not generate PWM signals.
PTMR does keep counting down after halting code execution
in Debug mode.
Fault-driven Wake-up from Idle mode does not function.
The Motor Control PWM module generates more interrupts
than expected when Doze mode is used and the output
postscaler value is different than 1:1.
The QEI module does not generate an interrupt in a particular
overflow condition.
Writing to the SPIxBUF register as soon as TBF bit is cleared
will cause the SPI module to ignore written data.
The UART module will not generate back-to-back Break
characters.
When Timer Gated Accumulation is enabled, the QEI does not
generate an interrupt on every falling edge.
When Timer Gated Accumulation is enabled, and an external
signal is applied, the POSCNT increments and generates an
interrupt after a match with MAXCNT.
programmed via PGECx/PGEDx pin pairs.
The SPI communication in Framed mode does not function
correctly if the Slave SPI frame delay bit (FRMDLY) is set to
‘1’.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
device may exceed the device data sheet specifications.
Issue Summary
PD
) of the
DS80447D-page 5
Revisions
A2 A3 A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)