DSPIC30F5016-30I/PT Microchip Technology, DSPIC30F5016-30I/PT Datasheet - Page 3
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC30F5016-30I/PT
Manufacturer Part Number
DSPIC30F5016-30I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F5016-30IPT.pdf
(230 pages)
2.DSPIC30F5016-30IPT.pdf
(14 pages)
3.DSPIC30F5016-30IPT.pdf
(6 pages)
4.DSPIC30F5016-30IPT.pdf
(18 pages)
Specifications of DSPIC30F5016-30I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
66KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F501630IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-30I/PT
Manufacturer:
MICROCHIP
Quantity:
624
Company:
Part Number:
DSPIC30F5016-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F5016-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
CAN
ADC
QEI
QEI
I
2
C
Only those issues indicated in the last column apply to the current silicon revision.
Accumulation
Accumulation
Consumption
Bus Collision
RX Filters 3,
Timer Gated
Timer Gated
SILICON ISSUE SUMMARY (CONTINUED)
Feature
in Sleep
4 and 5
Current
Mode
Mode
Mode
Number
Item
18.
19.
20.
21.
22.
When the I
generates a glitch on the SDA and SCL pins, causing a false
communication start in a single-master configuration or a bus
collision in a multi-master configuration.
CAN Receive filters 3, 4 and 5 may not work for a given
combination of instruction cycle speed and CAN bit time
quanta.
When Timer Gated Accumulation is enabled, the QEI does not
generate an interrupt on every falling edge.
When Timer Gated Accumulation is enabled, and an external
signal is applied, the POSCNT increments and generates an
interrupt after a match with MAXCNT.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
may exceed the device data sheet specifications.
2
C module is enabled, the dsPIC
Issue Summary
dsPIC30F5015/5016
®
DSC device
PD
) of the device
DS80452C-page 3
Revisions
Affected
A0
X
X
X
X
X
(1)