PIC18LF448-I/PT Microchip Technology, PIC18LF448-I/PT Datasheet - Page 19
![IC PIC MCU FLASH 8KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF448-I/PT
Manufacturer Part Number
PIC18LF448-I/PT
Description
IC PIC MCU FLASH 8KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18LF242-ISO.pdf
(36 pages)
2.PIC18F248-ISO.pdf
(402 pages)
3.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF448-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF448-I/PT
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18LF448-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
3.5
The Boot Block segment is programmed in exactly the
same manner as the ID locations (see Section 3.4).
Multi-panel writes must be disabled so that only
addresses in the range 0000h to 01FFh will be written.
The code sequence detailed in Figure 3-7 should be
used, except that the address data used in “Step 3” will
be in the range 000000h to 0001FFh.
TABLE 3-8:
FIGURE 3-9:
2010 Microchip Technology Inc.
Step 1: Direct access to config memory.
Step 2: Position the program counter
Step 3
Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
4-Bit
(2)
2: Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration
: Set Table Pointer for config byte to be written. Write even/odd addresses.
Boot Block Programming
code protection logic may prevent further table writes. To avoid this situation, move the program counter outside the
code protection area (e.g., GOTO 100000h).
bits. Always write all the configuration bits before enabling the write protection for configuration bits.
8E A6
8C A6
EF 00
F8 00
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
SET ADDRESS POINTER TO CONFIGURATION LOCATION
CONFIGURATION PROGRAMMING FLOW
Data Payload
Delay P9 Time
Configuration
Load Even
for Write
Program
Address
Done
Start
LSB
(1)
.
BSF
BSF
GOTO
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
INCF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
EECON1, EEPGD
EECON1, CFGS
100000h
3.6
Unlike code memory, the configuration bits are pro-
grammed a byte at a time. The “Table Write, Begin Pro-
gramming” (4-bit command, ‘1111’) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses,
and the MSB will be written to odd addresses. The
code
configuration locations is shown in Figure 3-8.
sequence
Core Instruction
Configuration Bits Programming
Delay P9 Time
PIC18FXX2/XX8
Configuration
Load Odd
for Write
Program
Address
Done
Start
MSB
to
program
two
DS39576C-page 19
consecutive