DSPIC30F6012-20I/PF Microchip Technology, DSPIC30F6012-20I/PF Datasheet - Page 9

• Manufacturer Part Number: DSPIC30F6012-20I/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012-20I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: 3-Wire/AC97/CAN/I2C/I2S/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F601220IPF

EXAMPLE 11:
FIGURE 1:
© 2008 Microchip Technology Inc.
BCLR
MOV
RRC
RRC
MOV
MOV
MOV
RRC
RRC
MOV
MOV
CSCK
COFS
Data
Note 1: The Slave mode operation shown in this figure uses the DCI module’s operation with DJST = 1, to create a
SR, #C
My1stTxDataWord, W0
W0, W0
W1, W1
W0, TXBUF0
W1, TXBUF1
My2ndTxDataWord, W0
W0, W0
W1, W1
W0, TXBUF2
W1, TXBUF3
2: Note that the actual data intended for transmission on Time Slot 0 is now straddled across two time slots –
3: Data loaded into TXBUF0 contains 15 MSbs of the actual 16-bit data to be transmitted, while the MSb of
4: Not all serial clock pulses are shown in this timing diagram.
work around for the erratum associated with the DCI module when DJST = 0.
Time Slot 0 and Time Slot 1. The MSb of Time Slot 0 is ‘0’; while the MSb of Time Slot 1 is actually the LSb
of the data intended for transmission.
TXBUF0 is cleared.
DCI SLAVE WORK AROUND
DCI SLAVE WORK AROUND
0
MSB
Data from TXBUF0
Time Slot 0
Actual Data to be transmitted
dsPIC30F6011/6012/6013/6014
Frame Synch and first data bit sampled here
LSB
+ 1
LSB
Data from TXBUF1
Time Slot 1
DS80198J-page 9