EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 26

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

EP9302
High Speed ARM9 System-on-Chip Processor with MaverickCrunch
Ethernet MAC Interface
STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer
(PHY) interface to the wireless medium.
PHY - Ethernet physical layer interface.
26
TXCLK cycle time
TXCLK high time
TXCLK low time
TXCLK to signal transition delay time
TXCLK rise/fall time
RXCLK cycle time
RXCLK high time
RXCLK low time
RXDVAL / RXERR setup time
RXDVAL / RXERR hold time
RXCLK rise/fall time
MDC cycle time
MDC high time
MDC low time
MDC rise/fall time
MDIO setup time (STA sourced)
MDIO hold time (STA sourced)
MDC to MDIO signal transition delay time
(PHY sourced)
Parameter
Copyright 2004 Cirrus Logic (All Rights Reserved)
Symbol
t
t
t
MDC_high
t
t
MDC_low
MDC_per
t
t
t
t
RX_high
t
t
t
TX_high
t
RX_low
TX_per
TX_low
RX_per
MDIOs
MDIOh
MDIOd
MDCrf
t
t
t
t
t
RXh
RXrf
TXd
TXrf
RXs
10 Mbit
mode
140
140
140
140
400
160
160
10
10
10
10
0
-
-
-
-
-
-
Min
100 Mbit
mode
400
160
160
14
14
14
14
10
10
10
10
0
-
-
-
-
-
-
10 Mbit
mode
400
200
200
400
200
200
10
15
15
-
-
-
-
-
-
-
-
-
Typ
100 Mbit
mode
40
20
20
10
40
20
20
15
15
-
-
-
-
-
-
-
-
-
10 Mbit
mode
260
260
260
260
300
25
5
5
5
-
-
-
-
-
-
-
-
-
Max
100 Mbit
mode
300
26
26
25
26
26
5
5
5
-
-
-
-
-
-
-
-
-
DS653PP2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns