EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 45

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

Ethernet MAC Interface
STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer
(PHY) interface to the wireless medium.
PHY - Ethernet physical layer interface.
DS638F2
TXCLK cycle time
TXCLK high time
TXCLK low time
TXCLK to signal transition delay time
TXCLK rise/fall time
RXCLK cycle time
RXCLK high time
RXCLK low time
RXDVAL / RXERR setup time
RXDVAL / RXERR hold time
RXCLK rise/fall time
MDC cycle time
MDC high time
MDC low time
MDC rise/fall time
MDIO setup time (STA sourced)
MDIO hold time (STA sourced)
MDC to MDIO signal transition delay time
(PHY sourced)
Parameter

Copyright 2010 Cirrus Logic (All Rights Reserved)
Symbol
t
t
t
MDC_high
t
t
MDC_per
MDC_low
t
t
t
t
t
t
TX_high
RX_high
t
t
TX_per
TX_low
RX_per
RX_low
MDIOs
MDIOh
MDIOd
MDCrf
t
t
t
t
t
RXrf
TXd
TXrf
RXs
RXh
10 Mbit
mode
140
140
140
140
160
160
10
10
10
10
0
-
-
-
-
-
-
-
Min
100 Mbit
mode
160
160
14
14
14
14
10
10
10
10
0
-
-
-
-
-
-
-
10 Mbit
mode
400
200
200
400
200
200
400
10
-
-
-
-
-
-
-
-
-
-
Enhanced Universal Platform SOC Processor
Typ
100 Mbit
mode
400
40
20
20
10
40
20
20
-
-
-
-
-
-
-
-
-
-
10 Mbit
mode
260
260
260
260
300
25
5
5
5
-
-
-
-
-
-
-
-
-
Max
100 Mbit
mode
300
26
26
25
26
26
5
5
5
-
-
-
-
-
-
-
-
-
EP9315
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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