Z8PE003SZ010SC Zilog, Z8PE003SZ010SC Datasheet
Z8PE003SZ010SC
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Z8PE003SZ010SC Summary of contents
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FEATURES Part ROM RAM* Number (kb) (Bytes) Z8PE003 1 Note: *General-Purpose. Microcontroller Core Features • All Instructions Execute in one 1-µs Instruction Cycle with a 10-MHz Crystal • On-Chip OTP EPROM Memory • General-Purpose ...
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... Power connections follow conventional descriptions below: Connection Power and B Ground / GND CC ALU FLAGS WDT Register Pointer RAM Register File Port B I/O Figure 1. Functional Block Diagram ZiLOG Circuit Device GND V SS XTAL Machine Timing OTP Program Memory Program Counter POR & DS007500-Z8X0399 ...
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... ZiLOG Z8Plus Core Address Counter PGM + Test Mode Logic PGM ADCLK XTAL Figure 2. EPROM Programming Mode Block Diagram DS007500-Z8X0399 AD 9–0 AD 9–0 Address MUX AD 9–0 EPROM Option Bits ADCLR Z8Plus OTP Microcontroller D7–0 Data MUX D7–0 PP Z8PE003 Port A 3 ...
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... Table 1. Standard Programming Mode Function Port B, Pins 1,2,3,4,5 Port A, Pins 7,6,5,4 Port A, Pins 3,2,1,0 Power Supply Ground Crystal Oscillator Clock Crystal Oscillator Clock Port B, Pin PB0 XTAL1 XTAL2 PA0 PA1 PA2 PA3 Direction Input/Output Input/Output Input/Output Output Input Input/Output DS007500-Z8X0399 ZiLOG ...
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... ZiLOG Pin # Symbol 1 PGM 2–4 GND 5 ADCLR/V PP 6–9 D7–D4 10–13 D3– GND XTAL1 18 ADCLK DS007500-Z8X0399 1 PGM GND GND GND 18-Pin ADCLR/V PP DIP/SOIC Figure 4. 18-Pin DIP/SOIC Pin Identification Table 2. EPROM Programming Mode Function Program Mode Ground Clear Clock/Program Voltage Data 7,6,5,4 ...
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... Table 3. Standard Programming Mode Function Port B, Pins 1,2,3,4,5 No Connection Port A, Pins 7,6,5,4 Port A, Pins 3,2,1,0 No Connection Power Supply Ground Crystal Oscillator Clock Crystal Oscillator Clock Port B, Pin PB0 XTAL1 XTAL2 PA0 PA1 PA2 PA3 Direction Input/Output Input/Output Input/Output Output Input Input/Output DS007500-Z8X0399 ZiLOG ...
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... ZiLOG Figure 6. 20-Pin SSOP Pin Identification/EPROM Programming Mode Pin # Symbol 1 PGM 2–4 GND 5 ADCLR 7–10 D7–D4 11–14 D3– GND XTAL1 20 ADCLK DS007500-Z8X0399 PGM 1 20 GND GND GND 20-Pin ADCLR/V PP SSOP Table 4. EPROM Programming Mode Function Program Mode Ground Clear Clock/Program Voltage ...
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... Min –40 –65 –0.6 SS –0.3 SS –0 –600 –600 . DD can affect device reliability. Total power dissipation should not exceed 880 mW for the package. Power dissipation is calculated as follows: Total Power Dissipation = ZiLOG Max Units Note +105 C +150 880 ...
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... ZiLOG STANDARD TEST CONDITIONS The characteristics listed below apply for standard test con- ditions as noted. All voltages are referenced to Ground. Pos- itive current flows into the referenced pin (Figure 7). CAPACITANCE T = 25º GND = 0V 1.0 MHz, unmeasured pins returned to GND Parameter Input capacitance ...
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... Driven by External Clock Generator 0.7 V Driven by External Clock Generator 1.5 V Driven by External Clock Generator 1.3 V 2.5 V 0.7 V 1 –2 4 – 10.0 mV 10.0 mV 0.064 µ 0V 0.064 µ 0V 0.114 µ 0V 0.114 µ 0V 200 kOhm 200 2.60 V DS007500-Z8X0399 ZiLOG Notes ...
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... ZiLOG Table 5. DC Electrical Characteristics (Continued) Sym Parameter I Supply Current CC I Standby Current CC1 I Standby Current CC2 Notes: 1. The V voltage specification of 3.0V guarantees 3.0V; the Typical values are measured For the analog comparator input when the analog comparator is enabled protection diode is provided from the pin ...
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... Driven by External Clock Generator 1.5 V Driven by External Clock Generator 2.5 V 2.5 V 1.5 V 1 –2 4 – 10.0 mV 10.0 mV <1.0 µ 0V <1.0 µ 0V <1.0 µ 0V <1.0 µ 0V 200 kOhm 200 2. MHz 4 MHz DS007500-Z8X0399 ZiLOG Notes 5,6 5,6 ...
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... ZiLOG Table 6. DC Electrical Characteristics (Continued) V Sym Parameter I Standby Current 4.5V CC1 5.5V I Standby Current 4.5V CC2 5.5V Notes: 1. The V voltage specification of 4.5V and 5.5V guarantees 5.0V ±0.5V Typical values are measured For analog comparator input when analog comparator is enabled. ...
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... T 5.5V voltage specification of 5.5V guarantees 5.0V DD for a logical 1 and 0.2 V for a logical 0ºC to +70º –40ºC to +105º MHz Min Max Units 100 DC 100 5TpC 5TpC 25 25 5TpC 5TpC OST DS007500-Z8X0399 ZiLOG Notes ± 0.5V. ...
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... ZiLOG Z8PLUS CORE The device is based on the ZiLOG Z8Plus Core Architec- ture. This core is capable of addressing up to 64KB of pro- gram memory and RAM. Register RAM is accessed as either 8- or 16-bit registers using a combination of 4-, 8-, and 12-bit addressing modes. The architecture supports RESET This section describes the Z8Plus reset conditions, reset timing, and register initialization procedures ...
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... U Current sample of the input pin Comments following RESET. 0 Deactivates all port special functions after RESET. 0 Defines all bits as inputs in PortA after RESET. following RESET WDT enabled in HALT mode, WDT time-out at maximum value, STOP mode disabled. 0 All standard timers are disabled. DS007500-Z8X0399 ZiLOG ...
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... ZiLOG Clock Internal Reset 128 XTAL Clock Cycles TCTLHI D6,D5,D4 XTAL SMR (PB0) Figure 10. Reset Circuitry with POR, WDT, V DS007500-Z8X0399 10 XTAL CLOCK CYCLES Figure 9. Reset Timing 3 WDT Tap Select WDTRST ÷64 16-Bit Timer Watch-Dog Timer SMR Logic V /POR Z8PE003 Z8Plus OTP Microcontroller ...
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... IRET registers are to , disabling all interrupts. reset 00h value to the master enable bit. A value change should always be accomplished by issuing the structions. Care should be taken not to set or clear while the master enable is set. DS007500-Z8X0399 ZiLOG through are set and 7 following 1 and in- EI ...
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... ZiLOG Table 11. Interrupt Mask Register—IMASK (FBh) Bit R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Read W = Write X = Indeterminate U = Undefined/ Undetermined Bit Position R/W Value Description 7 Disables Interrupts 0 Enables Interrupts 1 6 Reserved, must Disables IRQ5 0 Enables IRQ5 1 4 Disables IRQ4 ...
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... ENABLE EPROM PROTECT/DIS- ABLE TESTMODE option not possible to read the code using a tester, programmer, or any other standard method result, ZiLOG is unable to test the EPROM memory at any time after customer delivery. 20 Nesting of Vectored Interrupts Nesting vectored interrupts allows higher priority requests to interrupt a lower priority request ...
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... ZiLOG WATCH-DOG TIMER The Watch-Dog Timer ( ) is a retriggerable one-shot WDT 16-bit timer that resets the device if it reaches its terminal count. The is driven by the WDT XTAL2 vide the longer time-out periods required in applications, the watch-dog timer is only updated every 64th clock cycle. ...
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... TpC 6. 131,072 TpC 13. 262,144 TpC 26. 524,288 TpC 52. 1,048,576 TpC 104. 2,097,152 TpC 209. 8,388,608 TpC 838.86 ms instruction. mode can also be exited via a RESET WDT ) time-out. In these cases, pro- , the reset restart address. 0020H DS007500-Z8X0399 ZiLOG , the device STOP . 0 and HALT activation ...
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... ZiLOG STOP MODE OPERATION The mode provides the lowest possible device stand- STOP by current. This instruction turns off the on-chip oscillator and internal system clock. To enter the STOP mode, the Z8Plus only requires a instruction not necessary to execute a immediately before the STOP instruction ...
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... Figure 12. Clock Circuit 24 and XTAL2 . The clock and its output is R option in the graphical ) oscillator. Figure RC C Figure 13. Z8Plus in RC Oscillator Mode Machine Clock (SCLK) (5 cycles per in- struction) Timer Clock (TCLK) WDT Clock Note: 4 MHz max. Glitch Filter XTAL2 XTAL1 V Pin SS DS007500-Z8X0399 ZiLOG 2 ...
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... ZiLOG OSCILLATOR OPERATION The Z8Plus MCU uses a Pierce oscillator with an internal feedback resistor (Figure 14). The advantages of this circuit are low-cost, large output signal, low-power level in the crystal, stability with respect low impedances (not disturbed by stray effects). Z8Plus XTAL1 XTAL2 Figure 14. Pierce Oscillator with ...
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... Depending on the operation frequency, the oscillator may require additional capacitors, Figure 16 and Figure 17. The capacitance values are de- pendent on the manufacturer’s crystal specifications power lines should be separated from the clock XTAL1 or XTAL2 Z8Plus PB0 Board Design Example (Top View) and , as illustrated DS007500-Z8X0399 ZiLOG (and the other ...
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... ZiLOG V Z8Plus XTAL1 XTAL2 Figure 16. Crystal/Ceramic Resonator Oscillator XTAL1 C 1 Z8Plus L XTAL2 C 2 Figure 17. LC Clock In most cases, the is 0 Ohms and R D specifications are determined and specified by the crys- DS007500-Z8X0399 tal/ceramic resonator manufacturer. The creased to decrease the amount of drive from the oscillator SS output to the crystal ...
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... Enable TCTLL0 (D5) 16-bit Down Counter T3AR T2AR Internal Data Bus Figure 19. 16-Bit Standard Timer 1 1 and 1 5.83 (10^ [ 55.2 pF and C = 55.2 pF and ) are provided, but they can only operate as T3 IRQ5 (T23) T2VAL DS007500-Z8X0399 ZiLOG C for 5.83 1 ...
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... ZiLOG T1ARHI T1 OSC/8 T0ARHI DS007500-Z8X0399 Internal Data Bus T1ARHI T1ARLO T1VAL (Not used 8-bit in this mode) Down Counter 8-bit (Not used Down in this mode) Counter T0ARHI T0ARLO T0VAL Internal Data Bus Figure 20. 8-Bit Standard Timers Internal Data Bus T1ARLO T1VAL High Side ...
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... Disabled Enabled 1 1 Enabled Enabled 0 0 Enabled Enabled* Disabled 1 0 Disabled Enabled Enabled* Enabled* : (*) indicates auto-reload is active. OTE . 0 , the timer initializes to the changed value. operation. In all cases, the Z8Plus assigns a than to a decrementer WRITE of either register can be conducted at any READ DS007500-Z8X0399 ZiLOG ...
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... ZiLOG If a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach generated. In this case, a single interrupt is generated, and the interrupt corresponds to the even 8-bit timer. Example: Timers T2 and T3 are cascaded to form a single 16- bit timer. The interrupt for the combined timer is defined to be generated by timer T2 rather than T3 ...
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... No special functionality D4 D3 Comparator Interrupts --- --- -------------- ------------------- 0 0 Disabled Disabled 0 1 Enabled Disabled 1 0 Disabled Enabled 1 1 Enabled Enabled BIT 3: Comparator reference input BIT 4: Comparator signal input/IRQ0/IRQ2 Reserved (must Bit n set as output 0 = Bit n set as input Reserved (must be 0) PB1 T OUT OUT DS007500-Z8X0399 ZiLOG ...
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... ZiLOG RESET CONDITIONS After a , the timers are disabled. See Table 8 for timer RESET control, value, and auto-initialization register status after . RESET I/O PORTS The Z8Plus dedicates 14 lines to input and output. These lines are grouped into two ports known as Port A and Port B. Port 8-bit port, bit programmable as either inputs or outputs ...
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... Register 0D2H PTADIR Register configures the Figure 27. Port A Directional Control Register ZiLOG to any of the port registers with WRITEs ) should first be disabled. If this pre- SFR register should be the SFR SFR register SFR , Figure 26) ...
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... ZiLOG PORT A REGISTER DIAGRAMS Register 0D0H PTAIN Register 0D1H PTAOUT Register 0D2H PTADIR PTASFR Register 0D3H DS007500-Z8X0399 Port A Bit n current input value (only updated for pins in input mode) Figure 28. Port A Input Value Register Port A Bit n currentoutput value Figure 29. Port A Output Value Register ...
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... EPROM programming mode Enable PB0 as SMR Input Special Functionality 1 = Enable PB1 as T0 Output Special Functionality 1 = Enable PB2 as IRQ3 Input Special Functionality 1 = Analog Comparator on PB3 and PB4 0 = Digital Inputs on PB3 and PB4 1 = PB4 Interrupts Enabled 0 = PB4 Interrupts Disabled Reserved (must be 0) DS007500-Z8X0399 ZiLOG ...
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... ZiLOG PORT B—PIN 0 CONFIGURATION PTBIN Bit 0 SMR RESET PTBDIR Bit 0 PTBOUT Bit 0 PTBIN Bit 5 PTBDIR Bit 5 PTBOUT Bit 5 Note: There is no high-side protection device. The user should always place an external protection diode as shown. DS007500-Z8X0399 PTBDIR Bit 0 PTBSFR Bit 0 SMR Flag Figure 33. Port B Pin 0 Diagram ...
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... Z8PE003 Z8Plus OTP Microcontroller PORT B—PIN 1 CONFIGURATION PTBIN Bit 1 PTBDIR Bit 1 PTBOUT Bit Output X PTBSFR Bit 1 38 PTBDIR Bit 1 Figure 35. Port B Pin 1 Diagram ZiLOG PB1 PIN DS007500-Z8X0399 ...
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... ZiLOG PORT B—PIN 2 CONFIGURATION PTBIN Bit 2 IRQ3 PTBDIR Bit 2 PTBOUT Bit 2 DS007500-Z8X0399 PTBDIR Bit 2 Edge Detect Logic PTBSFR Bit 2 Figure 36. Port B Pin 2 Diagram Z8PE003 Z8Plus OTP Microcontroller PB2 PIN 39 ...
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... PORT B—PINS 3 AND 4 CONFIGURATION PTBIN Bit 4 IRQ1 Edge Detect Logic IRQ4 PTBSFR Bit 4 PTBIN Bit 3 PTBDIR Bit 3 PTBOUT Bit 3 PTBDIR Bit 4 PTBOUT Bit 4 40 PTBDIR Bit PTBSFR Bit 3 PTBDIR Bit 3 Figure 37. Port B Pins 3 and 4 Diagram ZiLOG REF PB3 PIN PB4 PIN DS007500-Z8X0399 ...
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... ZiLOG PORT B CONTROL REGISTERS Register 0D4H Register 0D5H Register 0D6H DS007500-Z8X0399 PTBIN Figure 38. Port B Input Value Register PTBOUT Figure 39. Port B Output Value Register PTBDIR Figure 40. Port B Directional Control Register Z8Plus OTP Microcontroller Port B Bit n current input value (only updated for pins in input mode) ...
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... Figure 41. Port B Special Function Register Enable PB0 as SMR Input Special Functionality 1 = Enable PB1 as T0 Output Special Functionality 1 = Enable PB2 as IRQ3 Input Special Functionality 1 = Analog Comparator on PB3 and PB4 0 = Digital Inputs on PB3 and PB4 1 = PB4 Interrupts Enabled 0 = PB4 Interrupts Disabled Reserved (must be 0) DS007500-Z8X0399 ZiLOG ...
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... ZiLOG I/O PORT RESET CONDITIONS Full Reset Port A and Port B output value registers are not affected by RESET . On , the Port A and Port B directional control reg- RESET isters are cleared to all zeros, which defines all pins in both ports as inputs the directional control registers redefine all pins ...
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... Figure 42. Typical Low Voltage Protection vs. Temperature 44 Low-Voltage Protection is active in only, but is disabled and RUN HALT STOP mode (Figure 42). Typical RUN and HALT modes 100 120 140 Temperature (ºC) DS007500-Z8X0399 ZiLOG modes ...
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... ZiLOG INPUT PROTECTION All I/O pins feature diode input protection. There is a diode from the I/O pad to and (Figure 43 PIN V SS Figure 43. I/O Pin Diode Input Protection DS007500-Z8X0399 However, the pin features only the input protection di- PB5 ode, from the pad to ...
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... Z8PE003 Z8Plus OTP Microcontroller PACKAGE INFORMATION 46 Figure 45. 18-Pin DIP Package Diagram Figure 46. 18-Pin SOIC Package Diagram ZiLOG DS007500-Z8X0399 ...
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... ZiLOG DS007500-Z8X0399 Figure 47. 20-Pin SSOP Package Diagram Z8PE003 Z8Plus OTP Microcontroller 47 ...
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... Z8PE003 Z8Plus OTP Microcontroller ORDERING INFORMATION Standard Temperature 18-Pin DIP Z8PE003PZ010SC 18-Pin SOIC Z8PE003SZ010SC 20-Pin SSOP Z8PE003HZ010SC Extended Temperature 18-Pin DIP Z8PE003PZ010EC 18-Pin SOIC Z8PE003SZ010EC 20-Pin SSOP Z8PE003CZ010EC Example: The Z8PE003PZ010SC is a 10-MHz DIP, 0ºC to 70ºC, with Plastic Standard Flow. ...