Z8F022ASJ020SC Zilog, Z8F022ASJ020SC Datasheet - Page 60
![IC ENCORE XP MCU FLASH 2K 28SOIC](/photos/6/91/69136/269-28-soic_sml.jpg)
Z8F022ASJ020SC
Manufacturer Part Number
Z8F022ASJ020SC
Description
IC ENCORE XP MCU FLASH 2K 28SOIC
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F022ASJ020SC
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
23
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3355
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F022ASJ020SC
Manufacturer:
Zilog
Quantity:
372
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Table 22. Port A–D High Drive Enable Sub-Registers (PxHDE)
Table 23. Port A–D Stop Mode Recovery Source Enable Sub-Registers (PxSMRE)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS022825-0908
PSMRE7
PHDE7
R/W
R/W
If 04H in Port A–D Address Register, accessible through the Port A–D Control Register
If 05H in Port A–D Address Register, accessible through the Port A–D Control Register
7
0
7
0
function). (Push-pull output)
1 = The source current for the associated pin is disabled (open-drain mode).
Port A–D High Drive Enable Sub-Registers
The Port A–D High Drive Enable sub-register
A–D Control register by writing
the Port A–D High Drive Enable sub-registers to 1 configures the specified port pins for
high current output drive operation. The Port A–D High Drive Enable sub-register affects
the pins directly and, as a result, alternate functions are also affected.
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–D Stop Mode Recovery Source Enable Sub-Registers
The Port A–D Stop Mode Recovery Source Enable sub-register
through the Port A–D Control register by writing
Setting the bits in the Port A–D Stop Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a Stop Mode Recovery source. During STOP mode,
any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
PSMRE[7:0]—Port Stop Mode Recovery Source Enabled
0 = The Port pin is not configured as a Stop Mode Recovery source. Transitions on this pin
PSMRE6
PHDE6
R/W
R/W
6
0
6
0
PSMRE5
PHDE5
R/W
R/W
5
5
0
0
PSMRE4
PHDE4
04H
R/W
R/W
4
0
4
0
to the Port A–D Address register. Setting the bits in
PSMRE3
PHDE3
R/W
R/W
(Table
3
3
0
0
05H
22) is accessed through the Port
to the Port A–D Address register.
Z8 Encore! XP
PSMRE2
PHDE2
R/W
R/W
2
0
2
0
General-Purpose Input/Output
(Table
Product Specification
PSMRE1
PHDE1
R/W
R/W
23) is accessed
1
1
0
0
®
F082A Series
PSMRE0
PHDE0
R/W
R/W
0
0
0
0
49
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