ST7FLITE09Y0B6 STMicroelectronics, ST7FLITE09Y0B6 Datasheet - Page 46
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ST7FLITE09Y0B6
Manufacturer Part Number
ST7FLITE09Y0B6
Description
MCU 8BIT 1.5KB FLASH 128KB 16DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITES2Y0B6.pdf
(124 pages)
Specifications of ST7FLITE09Y0B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
Processor Series
ST7FLITE0x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7FLIT0-IND/USB, ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
497-6250 - BOARD RGB COLOR CTRL STP04CM596497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5632-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FLITE09Y0B6
Manufacturer:
Maestro
Quantity:
1 200
Company:
Part Number:
ST7FLITE09Y0B6
Manufacturer:
STMicroelectronics
Quantity:
135
ST7LITE0xY0, ST7LITESxY0
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
10.3 UNUSED I/O PINS
Unused I/O pins must be connected to fixed volt-
age levels. Refer to
10.4 LOW POWER MODES
Table 11. Port Configuration
46/124
1
WAIT
HALT
Mode
Port A
Port B
Port
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
PA7
PA6:1
PA0
PB4
PB3
PB2:1
PB0
Pin name
Section
Description
13.8.
OR = 0
floating
floating
floating
floating
floating
floating
floating
Input (DDR=0)
pull-up interrupt
pull-up interrupt
pull-up interrupt
pull-up interrupt
10.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
10.6 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 30. Interrupt I/O Port State Transitions
The I/O port register configurations are summa-
rised as follows.
floating/pull-up
External interrupt on
selected external
event
OR = 1
pull-up
pull-up
pull-up
Interrupt Event
interrupt
INPUT
01
(reset state)
floating
INPUT
00
open drain
open drain
open drain
open drain
open drain
open drain
open drain
OR = 0
Event
Flag
Figure 30
-
Output (DDR=1)
open-drain
Control
Enable
OUTPUT
DDRx
ORx
Bit
10
XX
Other transitions
= DDR, OR
from
Wait
Exit
Yes
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
OR = 1
OUTPUT
push-pull
11
from
Exit
Halt
Yes