Z8F0813SH005EC Zilog, Z8F0813SH005EC Datasheet - Page 94
Z8F0813SH005EC
Manufacturer Part Number
Z8F0813SH005EC
Description
IC Z8 ENCORE MCU FLASH 8K 20SOIC
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F0813PH005SC.pdf
(227 pages)
Specifications of Z8F0813SH005EC
Core Processor
Z8
Core Size
8-Bit
Speed
5MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
269-3721
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BITS
FIELD
RESET
R/W
ADDR
PS025203-0405
TEN
R/W
0
7
Reserved—Must be 0.
PWMD—PWM Delay value
This field is a programmable delay to control the number of system clock cycles delay
before the Timer Output and the Timer Output Complement are forced to their active state.
INPCAP—Input Capture Event
This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture
Event.
Timer 0–1 Control Register 1
The Timer 0–1 Control (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
TEN—Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events
10 = Timer Interrupt only on defined Input Capture/Deassertion Events
11 = Timer Interrupt only on defined Reload/Compare Events
000 = No delay
001 = 2 cycles delay
010 = 4 cycles delay
011 = 8 cycles delay
100 = 16 cycles delay
101 = 32 cycles delay
110 = 64 cycles delay
111 = 128 cycles delay
0 = Previous timer interrupt is not a result of Timer Input Capture Event
1 = Previous timer interrupt is a result of Timer Input Capture Event
ONE-SHOT mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
TPOL
R/W
Table 56. Timer 0–1 Control Register 1 (TxCTL1)
6
0
R/W
5
0
P R E L I M I N A R Y
PRES
R/W
0
4
F07H, F0FH
R/W
3
0
Z8 Encore!
R/W
0
2
Product Specification
TMODE
®
R/W
1
0
Z8F0823 Series
R/W
0
0
Timers
77
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