Z16F2810VH20SG Zilog, Z16F2810VH20SG Datasheet - Page 177
Z16F2810VH20SG
Manufacturer Part Number
Z16F2810VH20SG
Description
IC ZNEO MCU FLASH 128K 68PLCC
Manufacturer
Zilog
Series
Encore!® ZNEOr
Specifications of Z16F2810VH20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
68-LCC (J-Lead)
Processor Series
Z16F2x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4536
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS022008-0810
address mismatch occurs.
11 = The LIN-UART generates an interrupt request on all received data bytes for which
MPEN—MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) mode.
0 = Disable MULTIPROCESSOR (9-bit) mode.
1 = Enable MULTIPROCESSOR (9-bit) mode.
MPBT—Multiprocessor Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled.
0 = Send 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send 1 in the multiprocessor bit location of the data stream (9th bit).
DEPOL—Driver Enable Polarity
0 = DE signal is active High.
1 = DE signal is active Low.
BRGCTL—Baud Rate Generator Control
This bit causes different LIN-UART behavior depending on whether the LIN-UART
receiver is enabled (
When the LIN-UART receiver is not enabled, this bit determines whether the baud rate
generator issues interrupts.
0 = BRG is disabled. Reads from the baud rate high and low byte registers return the BRG
1 = BRG is enabled and counting. The BRG generates a receive interrupt when it counts
When the LIN-UART receiver is enabled, this bit allows reads from the baud rate registers
to return the BRG count value instead of the Reload Value.
0 = Reads from the baud rate high and low byte registers return the BRG Reload Value.
1 = Reads from the baud rate high and low byte registers return the current BRG count
value. Unlike the timers, there is no mechanism to latch the High byte when the Low byte is
read.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the interrupt
1 = Received data does not generate an interrupt request to the interrupt controller. Only
IREN—Infrared Encoder/Decoder Enable
0 = Infrared encoder/decoder is disabled. LIN-UART operates normally.
1 = Infrared encoder/decoder is enabled. The LIN-UART transmits and receives data
down to 0. Reads from the baud rate high and low byte registers return the current
Reload Value.
BRG count value.
controller.
receiver errors generate an interrupt request.
through the Infrared encoder/decoder.
the most recent address byte matched the value in the address compare register.
REN
=
1
P R E L I M I N A R Y
in the LIN-UART control 0 register).
Product Specification
ZNEO
Z16F Series
LIN-UART
161
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