Z16F2811FI20SG Zilog, Z16F2811FI20SG Datasheet - Page 340
Z16F2811FI20SG
Manufacturer Part Number
Z16F2811FI20SG
Description
IC ZNEO MCU FLASH 128K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Specifications of Z16F2811FI20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F2x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4534
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F2811FI20SG
Manufacturer:
Zilog
Quantity:
155
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Table 175. Hardware Breakpoint Register (HWBPn)
PS022008-0810
BIT
FIELD
RESET
R/W
ADDR
BIT
FIELD
RESET
R/W
ADDR
Hardware Breakpoint Registers
R/W R/W R/W R/W
PC
31
15
0
The
PC—Break on Program Counter Match
This bit will enable the hardware breakpoint.
0 = Break on program counter match disabled.
1 = Break on program counter match enabled.
ST—Status
This bit is set when a hardware breakpoint occurs.
0 = No breakpoint occurred since this bit was last written to zero.
1 = Breakpoint has occurred or this bit written to one.
RD—Break on data read
This bit will enable the hardware watchpoint for data reads.
0 = Hardware watchpoint on read disabled.
1 = Hardware Watchpoint on read enabled.
WR—Break on data write
This bit will enable the hardware watchpoint for data writes.
0 = Hardware watchpoint on data write disabled.
1 = Hardware watchpoint on data write enabled.
MASK—Watchpoint address mask
The MASK field specifies the number of bits in ADDR to ignore when comparing against
addresses for read and write watchpoints. The mask is set to ignore 0 to 15 of the lower
address bits. This allows the watchpoint to monitor a memory block up to 32K in size.
ST
30
14
FF_E090-FF_E091,FF_E094-FF_E095,FF_E098-FF_E099,FF_E09C-FF_E09D
FF_E092-FF_E093,FF_E096-FF_E097,FF_E09A-FF_E09B,FF_E09E-FF_E09F
0
Hardware Breakpoint Register (HWBPn)
RD
29
13
0
WR
28
12
0
27
11
26
10
MASK
P R E L I M I N A R Y
0000
R/W
25
9
ADDR[15:0]
24
8
0000H
R/W
23
7
is used to set hardware breakpoints.
22
6
21
5
ADDR[23:16]
20
4
R/W
00H
Product Specification
ZNEO
19
3
On-Chip Debugger
18
2
Z16F Series
17
1
16
0
324
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