CY8CLED16P01-48LFXI Cypress Semiconductor Corp, CY8CLED16P01-48LFXI Datasheet - Page 3

• Manufacturer Part Number: CY8CLED16P01-48LFXI
• Description: IC PLC PSOC CMOS LED 16CH 48VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: PowerPSoC® CY8CLEDr

Specifications of CY8CLED16P01-48LFXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: LED, PLC, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 4x14b; D/A 4x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1.2.3 Coupling Circuit Reference Design
The coupling circuit couples low voltage signals from the
CY8CLED16P01 to the powerline. The topology of this circuit is
determined by the voltage on the powerline and design
constraints mandated by powerline usage regulations.
Cypress provides reference designs for a range of powerline
voltages including 110V/240V AC and 12V/24V AC/DC. The
CY8CLED16P01 is capable of data communication over other
AC/DC Powerlines as well with the appropriate external coupling
circuit. The 110V AC and 240V AC designs are compliant to the
following powerline usage regulations:
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1.3 Network Protocol
Cypress’s powerline optimized network protocol performs the
functions of the data link, network, and transport layers in an
ISO/OSI-equivalent model.
Figure 1-3. Powerline Network Protocol
The network protocol implemented on the CY8CLED16P01
supports the following features:
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Document Number: 001-49263 Rev. *E
FCC Part 15 for North America
EN 50065-1:2001 for Europe
Bidirectional half duplex communication
Master-slave or peer-to-peer network topologies
Multiple masters on powerline network
8-bit logical addressing supports up to 256 powerline nodes
16-bit extended logical addressing supports up to 65536
powerline nodes
64-bit physical addressing supports up to 2
Individual, broadcast or group mode addressing
Carrier Sense Multiple Access (CSMA)
Full control over transmission parameters
❐
❐
❐
PLC Core
Network Protocol
Physical Layer
Acknowledged
Unacknowledged
Repeated Transmit
FSK Modem
Powerline
Powerline Communication Solution
Powerline Transceiver Packet
Embedded Application
PSoC Core
System Resources
MAC, Decimator, I2C,
Additional System
Digital and Analog
Programmable
SPI, UART etc.
Resources
Peripherals
Controller
64
Communication
PrISM, PWM etc.
HB LED
DALI, DMX512
Technology
Modulation
Additional
powerline nodes
Interface
1.3.1 CSMA and Timing Parameters
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1.3.2 Powerline Transceiver Packet
The powerline network protocol defines a Powerline Transceiver
(PLT) packet structure, which is used for data transfers between
nodes across the powerline. Packet formation and data trans-
mission across the powerline network is implemented internally
in the CY8CLED16P01.
A PLT packet is divided into a variable length header (minimum
6 bytes to maximum 20 bytes, depending on address type),
variable length payload (minimum 0 bytes to maximum 31
bytes), and a packet CRC byte.
This packet (preceded by a one byte preamble "0xAB") is then
transmitted by the powerline modem PHY and the external
coupling circuit across the powerline.
The format of the PLT packet is shown in the following table.
Table 1-1. Powerline Transceiver (PLT) Packet Structure
Offset
Byte
0x00
0x01
0x02
0x03
0x04
0x05
0x06
CSMA – The protocol provides the random selection of a period
between 85 and 115 ms (out of seven possible values in this
range). Within this period, the Band-In-Use (BIU) detector must
indicate that the line is not in use, before attempting a trans-
mission.
BIU – A Band-In-Use detector, as defined under CENELEC EN
50065-1, is active whenever a signal that exceeds 86 dBμVrms
anywhere in the range 131.5 kHz to 133.5 kHz is present for
at least 4 ms. This threshold can be configured for different
end-system applications not requiring CENELEC
compliance.The modem tries to retransmit after every 85 to
115 ms when the band is in use. The transmitter times out after
1.1 seconds to 3 seconds (depending on the noise on the
Powerline) and generates an interrupt to indicate that the trans-
mitter was unable to acquire the powerline.
Type
SA
(8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical)
(8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical)
7
RSVD
DA Type Service
Seq Num
6
Powerline Transceiver Packet CRC
5
Payload (0 to 31 Bytes)
Type
Destination Address
4
Source Address
Command
Bit Offset
RSVD RSVD Response RSVD
Powerline Packet Header CRC
3
CY8CLED16P01
Payload Length
2
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