C8051T604-GS Silicon Laboratories Inc, C8051T604-GS Datasheet - Page 25

IC 8051 MCU 2K-EEPROM 14-SOIC

C8051T604-GS

Manufacturer Part Number
C8051T604-GS
Description
IC 8051 MCU 2K-EEPROM 14-SOIC
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Datasheet

Specifications of C8051T604-GS

Program Memory Type
OTP
Program Memory Size
2KB (2K x 8)
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SMBus/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T600DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1404 - KIT DEV FOR C8051T60X MCU'S
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1659-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T604-GS
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
C1
E
mask and the metal pad is to be 60 m minimum, all the way around the pad.
to assure good solder paste release.
Body Components.
Figure 5.2. SOIC-14 Recommended PCB Land Pattern
Table 5.2. SOIC-14 PCB Land Pattern Dimensions
5.30
Min
1.27 BSC
Max
5.40
Rev. 1.2
Dimension
C8051T600/1/2/3/4/5/6
X1
Y1
0.50
1.45
Min
1.55
Max
0.60
25

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