C8051T635-GM Silicon Laboratories Inc, C8051T635-GM Datasheet
C8051T635-GM
Manufacturer Part Number
C8051T635-GM
Description
IC MCU 2KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T635-GM
Program Memory Type
OTP
Program Memory Size
2KB (2K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
Package
20QFN EP
Device Core
8051
Family Name
C8051T63x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1463-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T635-GM
Manufacturer:
Silicon
Quantity:
750
Analog Peripherals
Comparator
-
-
-
Memory
-
-
On-Chip Debug
-
-
Supply Voltage 1.8 to 3.6 V
-
-
Temperature Range: –40 to +85 °C
Development Kit: C8051T630DK
Small Form Factor
C2CK/RST
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (< 0.5 µA)
768 bytes data RAM
2 kB EPROM OTP code memory (byte programmable)
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
C8051F336 can be used as in-system code development platform; com-
plete development kit available
On-chip LDO regulator for core supply
On-chip voltage supply monitor
GND
VDD
Peripheral Power
Programming
C2D
Power On
Hardware
Regulator
Debug /
EXTCLK
Reset
Reset
Core Power
Low-Freq.
24.5 MHz
Precision
Oscillator
Oscillator
Oscillator
Controller Core
External
System Clock
Program Memory
Circuit
Configuration
CIP-51 8051
2k Byte EPROM
256 Byte SRAM
512 Byte XRAM
Copyright © 2008 by Silicon Laboratories
SYSCLK
SFR
Bus
25 MIPS, 2 kB EPROM, Mixed-Signal MCU
High-Speed 8051 µC Core
-
-
-
Digital Peripherals
-
-
-
-
-
-
-
-
-
-
Package
-
-
Timers 0,
Clock Sources
SMBus
1, 2, 3
UART
Analog Peripherals
PCA/
WDT
Digital Peripherals
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
17 port I/O; All 5 V tolerant with high sink current
Hardware enhanced UART, SPI™, and SMBus™ serial ports
Four general purpose 16-bit counter/timers
Timer with Real-time clock capability
16-Bit programmable counter array (PCA) with five capture/compare
modules
Software timer
Two internal oscillators:
External oscillator: RC, C, or Clock
Can switch between clock sources on-the-fly
20-pin QFN
Pin Compatibile with C8051F33x Family of Devices
SPI
Port I/O Configuration
CP0, CP0A
-
-
-
-
-
-
Crossbar Control
24.5 MHz with ±2% accuracy supports crystal-less UART operation
Low-power suspend mode with fast wake time
80 kHz low frequency, low-power
PWM
Rising / falling edge capture
Frequency output
Comparator
+
Crossbar
-
Decoder
Priority
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
C8051T635
P0.0/VREF
P0.1/IDA0
P0.2/VPP
P0.3/EXTCLK
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0/C2D
1.21.2008
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