C8051F834-GS Silicon Laboratories Inc, C8051F834-GS Datasheet - Page 231
![IC MCU 8BIT 4KB FLASH 16SOIC](/photos/6/80/68073/16-soic__3_9mmwidth__sml.jpg)
C8051F834-GS
Manufacturer Part Number
C8051F834-GS
Description
IC MCU 8BIT 4KB FLASH 16SOIC
Manufacturer
Silicon Laboratories Inc
Series
C8051F83xr
Datasheet
1.C8051F800DK.pdf
(250 pages)
Specifications of C8051F834-GS
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (3.9mm Width)
Processor Series
C8051F8x
Core
8051
Data Bus Width
16 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F800DK
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1814-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F834-GS
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
Company:
Part Number:
C8051F834-GS
Manufacturer:
SILICON
Quantity:
1 897
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29.3.3. High-Speed Output Mode
In high-speed output mode, a module’s associated CEXn pin is toggled each time a match occurs between
the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a
match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is gen-
erated if the CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hard-
ware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the
TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the high-speed output mode. If ECOMn
is cleared, the associated pin will retain its state, and not toggle on the next match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
PCA0CPLn
Write to
Reset
PCA0CPHn
Write to
0
ENB
ENB
1
PCA
Timebase
Figure 29.6. PCA High-Speed Output Mode Diagram
Enable
P
W
M
1
6
n
x
C
O
M
E
n
PCA0CPLn
PCA0CPMn
C
A
P
P
n
0 0
PCA0L
C
A
P
N
n
16-bit Comparator
M
A
T
n
O
G
T
n
W
M
P
n
0 x
E
C
C
F
n
PCA0CPHn
PCA0H
Rev. 1.0
Match
Toggle
C
F
C
R
TOGn
0
1
PCA0CN
C8051F80x-83x
0
1
CEXn
C
C
F
2
C
C
F
1
C
C
F
0
PCA Interrupt
Crossbar
Port I/O
231
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