C8051F561-IM Silicon Laboratories Inc, C8051F561-IM Datasheet - Page 50
![IC 8051 MCU 32K FLASH 32-QFN](/photos/12/26/122666/c8051f561-im_sml.jpg)
C8051F561-IM
Manufacturer Part Number
C8051F561-IM
Description
IC 8051 MCU 32K FLASH 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F56xr
Specifications of C8051F561-IM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFN
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F560DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1695-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F561-IM
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F55x/56x/57x
6.1.4. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a very low power state between con-
versions. When Burst Mode is enabled, ADC0 wakes from a very low power state, accumulates 1, 4, 8, or
16 samples using an internal Burst Mode clock (approximately 25 MHz), then re-enters a very low power
state. Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conver-
sions then enter a very low power state within a single system clock cycle, even if the system clock is slow
(e.g., 32.768 kHz), or suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 6.4 shows an exam-
ple of Burst Mode Operation with a slow system clock and a repeat count of 4.
Important Note: When Burst Mode is enabled, only Post-Tracking and Dual-Tracking modes can be used.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
50
Convert Start
AD0INT Flag
AD0INT Flag
ADC0 State
ADC0 State
Time
Time
Figure 6.3. 12-Bit ADC Tracking Mode Example
Key
F
F
F
Sn
S1
S1
Track
Post-Tracking or Dual-Tracking Modes (AD0TK = ‘00')
Equal to one period of FCLK.
Each Sn is equal to one period of the SAR clock.
S2
S2
Convert
F
...
F
Rev. 1.1
S12
S1
Pre-Tracking Mode
S13
S2
Convert
F
...
S12
S13
F
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