C8051F715-GM Silicon Laboratories Inc, C8051F715-GM Datasheet - Page 169
![IC 8051 MCU 8K FLASH 48-QFN](/photos/12/26/122672/c8051f715-gm_sml.jpg)
C8051F715-GM
Manufacturer Part Number
C8051F715-GM
Description
IC 8051 MCU 8K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F71xr
Specifications of C8051F715-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1618-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F715-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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26. Watchdog Timer
The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. A WDT overflow
will force the MCU into the reset state. To prevent the reset, the WDT must be restarted by application soft-
ware before overflow. If the system experiences a software or hardware malfunction preventing the soft-
ware from restarting the WDT, the WDT will overflow and cause a reset.
Following a reset the WDT is automatically enabled and running with the default maximum time interval. If
desired the WDT can be disabled by system software or locked on to prevent accidental disabling. Once
locked, the WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by
this reset.
The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the
period between specific writes to its control register. If this period exceeds the programmed limit, a WDT
reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently
enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN)
shown in SFR Definition 26.1.
26.1. Enable/Reset WDT
The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica-
tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer
overflow. The WDT is enabled and reset as a result of any system reset.
26.2. Disable WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment
illustrates disabling the WDT:
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is
ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes.
26.3. Disable WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored
until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always
intending to use the watchdog should write 0xFF to WDTCN in the initialization code.
26.4. Setting WDT Interval
WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
4^(3+WDTCN[2-0]) x Tsysclk ;where T
For a 3 MHz system clock, this provides an interval range of 0.021 to 349.5 ms. WDTCN.7 must be logic 0
when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads 111b
after a system reset.
CLR EA
MOV WDTCN,#0DEh ; disable software watchdog timer
MOV WDTCN,#0ADh
SETB EA
; disable all interrupts
; re-enable interrupts
sysclk
is the system clock period.
Rev. 1.0
C8051F70x/71x
169
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