C8051F573-IM Silicon Laboratories Inc, C8051F573-IM Datasheet
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C8051F573-IM
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C8051F573-IM Summary of contents
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Analog Peripherals - 12-Bit ADC Up to 200 ksps • external single-ended inputs • VREF from on-chip VREF, external pin or V • Internal or external start of conversion source • Built-in temperature sensor • - Two ...
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C8051F55x/56x/57x 2 Rev. 1.1 ...
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Table of Contents 1. System Overview ..................................................................................................... 16 2. Ordering Information ............................................................................................... 20 3. Pin Definitions.......................................................................................................... 22 4. Package Specifications ........................................................................................... 28 4.1. QFN-40 Package Specifications........................................................................ 28 4.2. QFP-32 Package Specifications........................................................................ 30 4.3. QFN-32 Package Specifications........................................................................ 32 4.4. QFN-24 Package ...
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C8051F55x/56x/57x 12.2. Interrupts and SFR Paging .............................................................................. 95 12.3. SFR Page Stack Example ............................................................................... 97 13. Interrupts .............................................................................................................. 112 13.1. MCU Interrupt Sources and Vectors.............................................................. 112 13.1.1. Interrupt Priorities.................................................................................. 113 13.1.2. Interrupt Latency ................................................................................... 113 13.2. Interrupt Register Descriptions ...................................................................... ...
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Timing .......................................................................................................... 149 17.6.1. Multiplexed Mode .................................................................................. 151 18. Oscillators and Clock Selection ......................................................................... 155 18.1. System Clock Selection................................................................................. 155 18.2. Programmable Internal Oscillator .................................................................. 157 18.2.1. Internal Oscillator Suspend Mode ......................................................... 157 18.3. Clock Multiplier .............................................................................................. 160 18.4. ...
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C8051F55x/56x/57x 21.2.2. Message Object Interface Registers ..................................................... 212 21.2.3. Message Handler Registers.................................................................. 212 21.2.4. CAN Register Assignment .................................................................... 213 22. SMBus................................................................................................................... 216 22.1. Supporting Documents .................................................................................. 217 22.2. SMBus Configuration..................................................................................... 217 22.3. SMBus Operation .......................................................................................... 217 22.3.1. Transmitter Vs. Receiver....................................................................... ...
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Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 259 25.2. Timer 2 .......................................................................................................... 265 25.2.1. 16-bit Timer with Auto-Reload............................................................... 265 25.2.2. 8-bit Timers with Auto-Reload............................................................... 265 25.2.3. External Oscillator Capture Mode ......................................................... 266 25.3. Timer 3 .......................................................................................................... 271 25.3.1. ...
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C8051F55x/56x/57x List of Figures Figure 1.1. C8051F568-9 and ‘F570-5 (40-pin) Block Diagram .............................. 17 Figure 1.2. C8051F560-7 (32-pin) Block Diagram ................................................... 18 Figure 1.3. C8051F550-7 (24-pin) Block Diagram ................................................... 19 Figure 3.1. QFN-40 Pinout Diagram (Top View) ..................................................... 24 Figure ...
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Figure 16.1. Reset Sources ................................................................................... 136 Figure 16.2. Power-On and VDD Monitor Reset Timing ....................................... 137 Figure 17.1. Multiplexed Configuration Example ................................................... 147 Figure 17.2. EMIF Operating Modes ..................................................................... 148 Figure 17.3. Multiplexed 16-bit MOVX Timing ....................................................... 151 Figure 17.4. ...
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C8051F55x/56x/57x Figure 25.1. T0 Mode 0 Block Diagram ................................................................. 258 Figure 25.2. T0 Mode 2 Block Diagram ................................................................. 259 Figure 25.3. T0 Mode 3 Block Diagram ................................................................. 260 Figure 25.4. Timer 2 16-Bit Mode Block Diagram ................................................. 265 Figure 25.5. ...
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List of Tables Table 2.1. Product Selection Guide ......................................................................... 21 Table 3.1. Pin Definitions for the C8051F55x/56x/57x ............................................ 22 Table 4.1. QFN-40 Package Dimensions ................................................................ 28 Table 4.2. QFN-40 Landing Diagram Dimensions ................................................... 29 Table 4.3. QFP-32 Package Dimensions ................................................................ ...
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C8051F55x/56x/57x Table 22.3. Sources for Hardware Changes to SMB0CN ..................................... 225 Table 22.4. SMBus Status Decoding ..................................................................... 231 Table 23.1. Baud Rate Generator Settings for Standard Baud Rates ................... 234 Table 24.1. SPI Slave Timing Parameters ............................................................ 254 Table 26.1. ...
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List of Registers SFR Definition 6.4. ADC0CF: ADC0 Configuration ...................................................... 58 SFR Definition 6.5. ADC0H: ADC0 Data Word MSB .................................................... 59 SFR Definition 6.6. ADC0L: ADC0 Data Word LSB ...................................................... 59 SFR Definition 6.7. ADC0CN: ADC0 Control ................................................................ 60 SFR ...
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C8051F55x/56x/57x SFR Definition 16.2. RSTSRC: Reset Source ............................................................ 141 SFR Definition 17.1. EMI0CN: External Memory Interface Control ............................ 145 SFR Definition 17.2. EMI0CF: External Memory Configuration .................................. 146 SFR Definition 17.3. EMI0TC: External Memory Timing Control ................................ 150 SFR Definition ...
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SFR Definition 22.3. SMB0DAT: SMBus Data ............................................................ 226 SFR Definition 23.1. SCON0: Serial Port 0 Control .................................................... 238 SFR Definition 23.2. SMOD0: Serial Port 0 Control .................................................... 239 SFR Definition 23.3. SBUF0: Serial (UART0) Port Data Buffer .................................. 240 SFR ...
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C8051F55x/56x/57x 1. System Overview C8051F55x/56x/57x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted fea- tures are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. High-speed pipelined 8051-compatible microcontroller core ( ...
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Power On CIP-51 8051 Controller Reset Core (50 MHz) Reset Flash Program Memory Debug / C2CK/RST Programming 256 Byte RAM Hardware C2D 2 kB XRAM Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 XTAL2 ...
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C8051F55x/56x/57x Power On CIP-51 8051 Controller Reset Core (50 MHz) Reset Flash Program Memory Debug / C2CK/RST Programming 256 Byte RAM Hardware C2D 2 kB XRAM Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 ...
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Power On CIP-51 8051 Controller Reset Core (50 MHz) Reset Flash Program Memory Debug / C2CK/RST Programming 256 Byte RAM Hardware C2D 2 kB XRAM Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 XTAL2 ...
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C8051F55x/56x/57x 2. Ordering Information The following features are common to all devices in this family: 50 MHz system clock and 50 MIPS throughput (peak) 2304 bytes of RAM (256 internal bytes and 2048 XRAM bytes) 2 SMBus/I ...
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... C8051F566-IQ 16 QFN-24 C8051F567-IM 16 QFN-24 C8051F567-IQ 16 QFN-32 C8051F568-IM 32 QFP-32 C8051F569-IM 32 QFN-32 C8051F570-IM 32 QFP-32 C8051F571-IM 32 QFN-32 C8051F572-IM 16 QFP-32 C8051F573-IM 16 QFN-32 C8051F574-IM 16 QFP-32 C8051F575-IM 16 Rev. 1.1 25 — QFN-32 25 — QFP-32 — 25 — QFN-32 — 25 — QFP-32 — ...
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C8051F55x/56x/57x 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F55x/56x/57x Name Pin Pin 40-pin 32-pin packages packages VDD 4 4 GND 6 6 VDDA 5 5 GNDA 7 7 VREGIN 3 3 VIO 2 2 RST C2CK ...
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Table 3.1. Pin Definitions for the C8051F55x/56x/57x (Continued) Name Pin Pin 40-pin 32-pin 24-pin packages packages packages P1.7 27 ...
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... VIO 2 VREGIN 3 VDD 4 VDDA 5 GND 6 GNDA 7 P0.0 / VREF 8 P4.0 / C2D 9 RST / C2CK 10 Figure 3.1. QFN-40 Pinout Diagram (Top View) 24 C8051F568-IM C8051F569-IM C8051F570-IM C8051F571-IM C8051F572-IM C8051F573-IM C8051F574-IM C8051F575-IM (Top View) GND Rev. 1.1 30 P1.4 29 P1.5 28 P1.6 27 P1.7 26 P2.0 25 P2.1 24 P2.2 23 P2.3 22 P2.4 21 ...
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P0.1 / CNVSTR VIO 2 VREGIN 3 VDD 4 VDDA 5 6 GND 7 GNDA 8 P0.0 / VREF Figure 3.2. QFP-32 Pinout Diagram (Top View) C8051F55x/56x/57x C8051F560-IQ C8051F561-IQ C8051F562-IQ C8051F563-IQ C8051F564-IQ C8051F565-IQ C8051F566-IQ C8051F567-IQ (Top View) Rev. 1.1 ...
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C8051F55x/56x/57x P0.1 / CNVSTR 1 VIO 2 VREGIN 3 VDD 4 VDDA 5 GND 6 GNDA 7 P0.0 / VREF 8 Figure 3.3. QFN-32 Pinout Diagram (Top View) 26 C8051F560-IM C8051F561-IM C8051F562-IM C8051F563-IM C8051F564-IM C8051F565-IM C8051F566-IM C8051F567-IM (Top View) GND ...
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VIO 1 C8051F550-IM C8051F551-IM VREGIN 2 C8051F552-IM C8051F553-IM VDD 3 C8051F554-IM C8051F555-IM GND 4 C8051F556-IM C8051F557-IM GNDA 5 (Top View) P0.0/VREF 6 Figure 3.4. QFN-24 Pinout Diagram (Top View) C8051F55x/56x/57x 18 P0.7/CAN0 RX 17 P1.0 16 P1.1 15 P1.2 14 ...
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C8051F55x/56x/57x 4. Package Specifications 4.1. QFN-40 Package Specifications Figure 4.1. QFN-40 Package Drawing Table 4.1. QFN-40 Package Dimensions Dimension Min Typ A 0.80 0.85 A1 0.00 b 0.18 0.23 D 6.00 BSC D2 4.00 4.10 e 0.50 BSC E 6.00 ...
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Figure 4.2. QFN-40 Landing Diagram Table 4.2. QFN-40 Landing Diagram Dimensions Dimension Min C1 5.80 C2 5.80 e 0.50 BSC X1 0.15 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimension and Tolerancing is ...
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C8051F55x/56x/57x 4.2. QFP-32 Package Specifications Figure 4.3. QFP-32 Package Drawing Table 4.3. QFP-32 Package Dimensions Dimension Min Typ A — — A1 0.05 — A2 1.35 1.40 b 0.30 0.37 c 0.09 — D 9.00 BSC. D1 7.00 BSC. e ...
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Figure 4.4. QFP-32 Landing Diagram Table 4.4. QFP-32 Landing Diagram Dimensions Dimension Min C1 8.40 C2 8.40 E 0.80 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based ...
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C8051F55x/56x/57x 4.3. QFN-32 Package Specifications Figure 4.5. QFN-32 Package Drawing Table 4.5. QFN-32 Package Dimensions Dimension Min Typ A 0.80 0.9 A1 0.00 0.02 b 0.18 0.25 D 5.00 BSC. D2 3.20 3.30 e 0.50 BSC. E 5.00 BSC. Notes: ...
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Figure 4.6. QFN-32 Landing Diagram Table 4.6. QFN-32 Landing Diagram Dimensions Dimension Min C1 4.80 C2 4.80 e 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design ...
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C8051F55x/56x/57x 4.4. QFN-24 Package Specifications Figure 4.7. QFN-24 Package Drawing Table 4.7. QFN-24 Package Dimensions Dimension Min Typ A 0.70 0.75 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC D2 2.55 2.70 e 0.50 BSC E 4.00 BSC E2 ...
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Figure 4.8. QFN-24 Landing Diagram Table 4.8. QFN-24 Landing Diagram Dimensions Dimension Min C1 3.90 C2 3.90 E 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern ...
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C8051F55x/56x/57x 5. Electrical Characteristics 5.1. Absolute Maximum Specifications Table 5.1. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on V with Respect to GND REGIN Voltage on V with Respect to GND DD Voltage on VDDA with ...
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Electrical Characteristics Table 5.2. Global Electrical Characteristics –40 to +125 °C, 24 MHz system clock unless otherwise specified. Parameter Supply Input Voltage (V ) REGIN Digital Supply Voltage (V ) System Clock < 25 MHz DD System Clock > ...
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C8051F55x/56x/57x Table 5.2. Global Electrical Characteristics (Continued) –40 to +125 °C, 24 MHz system clock unless otherwise specified. Parameter Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash ...
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Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency Note: With system clock frequencies greater than 25 MHz, the V (VDMLVL = 1b in SFR VDM0CN) to prevent undefined CPU operation. The high threshold should only be used with ...
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C8051F55x/56x/57x Table 5.3. Port I/O DC Electrical Characteristics V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. DD Parameters Output High Voltage I = –3 mA, Port I/O push-pull –10 µA, Port I/O ...
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Table 5.4. Reset Electrical Characteristics –40 to +125 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current V RST Threshold ( RST-LOW V RST Threshold (V ...
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C8051F55x/56x/57x Table 5.6. Internal High-Frequency Oscillator Electrical Characteristics V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified; Using factory-calibrated settings. DD Parameter Oscillator Frequency IFCN = 111b; VDD > VREGMIN IFCN = 111b; VDD < VREGMIN ...
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Table 5.7. Clock Multiplier Electrical Specifications V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. DD Parameter Input Frequency (Fcm ) in Output Frequency Power Supply Current Table 5.8. Voltage Regulator Electrical Characteristics V = 1.8 ...
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C8051F55x/56x/57x Table 5.9. ADC0 Electrical Characteristics VDDA = 1.8 to 2.75 V, –40 to +125 °C, VREF = 1.5 V (REFSL=0) unless otherwise specified. Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity 1 Offset Error Full Scale Error Offset Temperature ...
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Table 5.10. Temperature Sensor Electrical Characteristics VDDA = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. Parameter Linearity Slope Slope Error* Offset Temp = 0 °C Offset Error* Temp = 0 °C Power Supply Current Tracking Time ...
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C8051F55x/56x/57x Table 5.12. Comparator 0 and Comparator 1 Electrical Characteristics VIO = 1.8 to 5.25 V, –40 to +125 °C unless otherwise noted. Parameter CPn+ – CPn– = 100 mV Response Time: * Mode 0, Vcm = 1.5 V CPn+ ...
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ADC (ADC0) The ADC0 on the C8051F55x/56x/57x consists of an analog multiplexer (AMUX0) with 33, 25 total input selections and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, programmable window detector, programmable attenuation (1:2), ...
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C8051F55x/56x/57x 6.1. Modes of Operation In a typical system, ADC0 is configured using the following steps gain adjustment is required, refer to Section “6.3. Selectable Gain” on page 53. 2. Choose the start of conversion source. 3. ...
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Post-Tracking Mode is selected when AD0TM is set to 01b. A programmable tracking time based on AD0TK is started immediately following the convert start signal. Conversions are started after the pro- grammed tracking time ends. After a conversion is complete, ...
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C8051F55x/56x/57x Convert Start Time F S1 ADC0 State AD0INT Flag Time F S1 ADC0 State Track AD0INT Flag Key F Sn Figure 6.3. 12-Bit ADC Tracking Mode Example 6.1.4. Burst Mode Burst Mode is a power saving feature that allows ...
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Similarly, the Window Comparator will not compare the result to the greater-than and less-than registers until “repeat count” conversions have been accumulated. Note: When using Burst Mode, care must be taken to issue a convert start signal no ...
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C8051F55x/56x/57x 6.2. Output Code Formatting The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code. When the repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the ...
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Figure 6.5. ADC0 Equivalent Input Circuit 6.3. Selectable Gain ADC0 on the C8051F55x/56x/57x family of devices implements a selectable gain adjustment option. ...
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C8051F55x/56x/57x For example, if ADC0GNH = 0xFC, ADC0GNL = 0x00, and GAINADD = 1, GAIN = 0xFC0 = 4032, and the resulting equation is as follows: 4032 ------------ - GAIN = 4096 The table below equates values in ...
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Setting the Gain Value The three programmable gain registers are accessed indirectly using the ADC0H and ADC0L registers when the GAINEN bit (ADC0CF.0) bit is set. ADC0H acts as the address register, and ADC0L is the data register. The ...
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C8051F55x/56x/57x Gain Register Definition 6.1. ADC0GNH: ADC0 Selectable Gain High Byte Bit 7 6 Name Type 1 1 Reset Indirect Address = 0x04; Bit Name 7:0 GAINH[7:0] ADC0 Gain High Byte. See Section 6.3.1 for details on calculating the value ...
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Gain Register Definition 6.3. ADC0GNA: ADC0 Additional Selectable Gain Bit 7 6 Name Reserved Reserved Reserved W W Type 0 0 Reset Indirect Address = 0x08; Bit Name 7:1 Reserved Must Write 0000000b. 0 GAINADD ADC0 Additional Gain Bit. Setting ...
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C8051F55x/56x/57x SFR Definition 6.4. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC; SFR Page = 0x00 Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from ...
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SFR Definition 6.5. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE; SFR Page = 0x00 Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0 and AD0RPT as ...
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C8051F55x/56x/57x SFR Definition 6.7. ADC0CN: ADC0 Control Bit 7 6 AD0EN BURSTEN AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; SFR Page = 0x00; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 ...
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SFR Definition 6.8. ADC0TK: ADC0 Tracking Mode Select Bit 7 6 AD0PWR[3:0] Name R/W Type 1 1 Reset SFR Address = 0xBA; SFR Page = 0x00 Bit Name 7:4 AD0PWR[3:0] ADC0 Burst Power-Up Time. For BURSTEN = 0: ADC0 Power ...
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C8051F55x/56x/57x SFR Definition 6.9. ADC0GTH: ADC0 Greater-Than Data High Byte Bit 7 6 Name Type 1 1 Reset SFR Address = 0xC4; SFR Page = 0x00 Bit Name 7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits. SFR Definition 6.10. ADC0GTL: ...
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SFR Definition 6.11. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6; SFR Page = 0x00 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 6.12. ADC0LTL: ADC0 ...
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C8051F55x/56x/57x ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (4095/4096) 0x0FFF not affected 0x0201 VREF x (512/4096) 0x0200 ADC0LTH:ADC0LTL 0x01FF 0x0101 VREF x (256/4096) 0x0100 ADC0GTH:ADC0GTL 0x00FF not affected 0x0000 0 Figure 6.6. ADC Window Compare Example: Right-Justified Data ADC0H:ADC0L ...
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ADC0 Analog Multiplexer ADC0 includes an analog multiplexer to enable multiple analog input sources. Any of the following may be selected as an input: P0.0 – P3.7, the on-chip temperature sensor, the core power supply (V (GND). ADC0 is ...
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C8051F55x/56x/57x SFR Definition 6.13. ADC0MX: ADC0 Channel Select Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xBB; SFR Page = 0x00; Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5:0 AMX0P[5:0] AMUX0 ...
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Temperature Sensor An on-chip temperature sensor is included on the C8051F55x/56x/57x devices which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the tempera- ture sensor, the ADC multiplexer channel should ...
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C8051F55x/56x/57x 7. Voltage Reference The Voltage reference multiplexer on the C8051F55x/56x/57x devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator routed to the VREF pin, or the V power supply voltage (see Figure 7.1). ...
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SFR Definition 7.1. REF0CN: Reference Control Bit 7 6 ZTCEN Name R R Type 0 0 Reset SFR Address = 0xD1; SFR Page = 0x00 Bit Name 7:6 Unused Read = 00b; Write = don’t care. 5 ZTCEN Zero Temperature ...
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C8051F55x/56x/57x 8. Comparators The C8051F55x/56x/57x devices include two on-chip programmable voltage Comparators. A block dia- gram of the comparators is shown in Figure 8.1, where “n” is the comparator number (0 or 1). The two Comparators operate identically except that ...
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Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous output is available ...
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C8051F55x/56x/57x Note that false rising edges and falling edges can be detected when the comparator is first powered changes are made to the hysteresis or response time control bits. Therefore recommended that the rising-edge and ...
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SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9B; SFR Page = 0x00 Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 ...
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C8051F55x/56x/57x SFR Definition 8.3. CPT1CN: Comparator1 Control Bit 7 6 CP1EN CP1OUT CP1RIF Name R/W R Type 0 0 Reset SFR Address = 0x9D; SFR Page = 0x00 Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 ...
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SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection Bit 7 6 CP1RIE Name R R Type 0 0 Reset SFR Address = 0x9E; SFR Page = 0x00 Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP1RIE Comparator1 ...
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C8051F55x/56x/57x 8.1. Comparator Multiplexer C8051F55x/56x/57x devices include an analog input multiplexer for each of the comparators to connect Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 8.5). The CMX0P3 – ...
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SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection Bit 7 6 CMX0N[3:0] Name R/W Type 0 1 Reset SFR Address = 0x9C; SFR Page = 0x00 Bit Name 7:4 CMX0N[3:0] Comparator0 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: 0101: ...
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C8051F55x/56x/57x SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection Bit 7 6 CMX1N[3:0] Name R/W Type 0 1 Reset SFR Address = 0x9F; SFR Page = 0x00 Bit Name 7:4 CMX1N[3:0] Comparator1 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: ...
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Voltage Regulator (REG0) C8051F55x/56x/57x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0 at the V pin can be as high as 5.25 V. The output can be selected by software to 2 ...
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C8051F55x/56x/57x V DD 4.7 µF Figure 9.2. External Capacitors for Voltage Regulator Input/Output—Regulator Disabled SFR Definition 9.1. REG0CN: Regulator Control Bit 7 6 REGDIS Reserved Name R/W R/W Type 0 1 Reset SFR Address = 0xC9; SFR Page = 0x00 ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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C8051F55x/56x/57x ACCUMULATOR PSW PROGRAM COUNTER (PC) PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP IDLE Figure 10.1. CIP-51 Block Diagram With the CIP-51's maximum system clock at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has ...
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Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary ...
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C8051F55x/56x/57x Table 10.1. CIP-51 Instruction Set Summary Mnemonic Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ...
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Table 10.1. CIP-51 Instruction Set Summary (Continued) Mnemonic XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A RL ...
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C8051F55x/56x/57x Table 10.1. CIP-51 Instruction Set Summary (Continued) Mnemonic SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C, bit AND direct bit to Carry ANL C, /bit AND complement ...
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Notes on Registers, Operands and Addressing Modes: Rn —Register R0–R7 of the currently selected register bank. @Ri —Data RAM location addressed indirectly through R0 or R1. rel —8-bit, signed (two’s complement) offset relative to the first byte of the following ...
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C8051F55x/56x/57x SFR Definition 10.1. DPL: Data Pointer Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x82; SFR Page = All Pages Bit Name 7:0 DPL[7:0] Data Pointer Low. The DPL register is the low byte ...
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SFR Definition 10.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81; SFR Page = All Pages Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the ...
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C8051F55x/56x/57x SFR Definition 10.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set ...
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Serial Number Special Function Registers (SFRs) The C8051F55x/56x/57x devices include four SFRs, SN0 through SN3, that are pre-programmed during production with a unique, 32-bit serial number. The serial number provides a unique identification number for each device and can ...
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C8051F55x/56x/57x 11. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...
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C8051F550/1/2/3 C8051F560/1/2/3/8/9 C8051F570/1 0x7FFF Reserved Area 0x7C00 Lock Byte 0x7BFF 0x7BFE Lock Byte Page 0x7A00 Flash Memory Space (32 kB Flash Device) 0x0000 Figure 11.2. Flash Program Memory Map 11.1.1. MOVX Instruction and Program Memory The MOVX instruction in an ...
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C8051F55x/56x/57x upper 128 bytes of data memory. Figure 11.1 illustrates the data memory organization of the C8051F55x/56x/57x. 11.2.1.1. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051F55x/56x/57x's resources and peripherals. The CIP-51 controller core duplicates the SFRs found ...
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C8051F55x/56x/57x Interrupt Logic CIP-51 Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). This function defaults to ...
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SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Control register is left in the default enabled state (i.e., SFRPGEN = 1), and ...
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C8051F55x/56x/57x While CIP-51 executes in-line code (writing values to SPI0DAT in this example), the CAN0 Interrupt occurs. The CIP-51 vectors to the CAN0 ISR and pushes the current SFR Page value (SFR Page 0x00) into SFRNEXT in the SFR Page ...
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While in the CAN0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the CAN0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the high ...
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C8051F55x/56x/57x On exit from the PCA interrupt service routine, the CIP-51 will return to the CAN0 ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be automatically popped off of the SFR ...
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On the execution of the RETI instruction in the CAN0 ISR, the value in SFRPAGE register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the SPI0DAT register as it did prior to the interrupts occurring. See ...
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C8051F55x/56x/57x SFR Definition 12.1. SFR0CN: SFR Page Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x84; SFR Page = 0x0F Bit Name 7:1 Unused Read = 0000000b; Write = Don’t Care 0 SFRPGEN SFR ...
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SFR Definition 12.2. SFRPAGE: SFR Page Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA7; SFR Page = All Pages Bit Name 7:0 SFRPAGE[7:0] SFR Page Bits. Represents the SFR Page the C8051 core uses when reading ...
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C8051F55x/56x/57x SFR Definition 12.3. SFRNEXT: SFR Next Bit 7 6 Name Type 0 0 Reset SFR Address = 0x85; SFR Page = All Pages Bit Name 7:0 SFRNEXT[7:0] SFR Page Bits. This is the value that will go to the ...
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SFR Definition 12.4. SFRLAST: SFR Last Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA7; SFR Page = All Pages Bit Name 7:0 SFRLAST[7:0] SFR Page Stack Bits. This is the value that will go to the ...
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C8051F55x/56x/57x Table 12.1. Special Function Register (SFR) Memory Map for Pages 0x00 and 0x0F 0(8) 1(9) 2( SPI0CN PCA0L PCA0H F SN0 SN1 P0MAT P0MASK F (All Pages) P0MDIN P1MDIN E8 0 ADC0CN PCA0CPL1 PCA0CPH1 ...
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Table 12.2. Special Function Register (SFR) Memory Map for Page 0x0C 0(8) 1(9) 2(A) F8 CAN0IF2DA2L CAN0IF2DA2H CAN0IF2DB1L CAN0IF2DB1H CAN0IF2DB2L F0 B CAN0IF2A2L (All Pages) E8 CAN0IF2M1L CAN0IF2M1H CAN0IF2M2L CAN0IF2M2H E0 ACC CAN0IF2CML CAN0IF2CMH (All Pages) D8 CAN0IF1DB1L CAN0IF1DB1H CAN0IF1DB2L ...
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C8051F55x/56x/57x Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 ...
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Table 12.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address IT01CF 0xE4 INT0/INT1 Configuration LIN0ADR 0xD3 LIN0 Address LIN0CF 0xC9 LIN0 Configuration LIN0DAT 0xD2 LIN0 Data OSCICN 0xA1 Internal Oscillator ...
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C8051F55x/56x/57x Table 12.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address PCA0CPH1 0xEA PCA Capture 1 High PCA0CPH2 0xEC PCA Capture 2 High PCA0CPH3 0xEE PCA Capture 3 High PCA0CPH4 ...
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Table 12.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SMB0CF 0xC1 SMBus0 Configuration SMB0CN 0xC0 SMBus0 Control SMB0DAT 0xC2 SMBus0 Data SMOD0 0xA9 UART0 Mode SN0 0xF9 Serial Number ...
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C8051F55x/56x/57x 13. Interrupts The C8051F55x/56x/57x devices include an extended interrupt system supporting a total of 18 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and exter- nal inputs pins varies according to the specific ...
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Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be ...
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C8051F55x/56x/57x Table 13.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B ADC0 ...
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Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described in this section. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions ...
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C8051F55x/56x/57x SFR Definition 13.1. IE: Interrupt Enable Bit 7 6 Name EA ESPI0 Type R/W R/W Reset 0 0 SFR Address = 0xA8; Bit-Addressable; SFR Page = All Pages Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. ...
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SFR Definition 13.2. IP: Interrupt Priority Bit 7 6 Name PSPI0 Type R R/W Reset 1 0 SFR Address = 0xB8; Bit-Addressable; SFR Page = All Pages Bit Name 7 Unused Read = 1b, Write = Don't Care. 6 PSPI0 ...
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C8051F55x/56x/57x SFR Definition 13.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 Name ELIN0 ET3 Type R/W R/W Reset 0 0 SFR Address = 0xE6; SFR Page = All Pages Bit Name 7 ELIN0 Enable LIN0 Interrupt. This bit sets ...
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SFR Definition 13.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 Name PLIN0 PT3 Type R/W R/W Reset 0 0 SFR Address = 0xF6; SFR Page = 0x00 and 0x0F Bit Name 7 PLIN0 LIN0 Interrupt Priority Control. This bit ...
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C8051F55x/56x/57x SFR Definition 13.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xE7; SFR Page = All Pages Bit Name 7:3 Unused Read = 00000b; Write = Don’t Care. 2 ...
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SFR Definition 13.6. EIP2: Extended Interrupt Priority Enabled 2 Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xF7; SFR Page = 0x00 and 0x0F Bit Name 7:3 Unused Read = 00000b; Write = Don’t Care. ...
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C8051F55x/56x/57x 13.3. External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select ...
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SFR Definition 13.7. IT01CF: INT0/INT1 Configuration Bit 7 6 Name IN1PL IN1SL[2:0] Type R/W Reset 0 0 SFR Address = 0xE4; SFR Page = 0x0F Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input ...
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C8051F55x/56x/57x 14. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the ...
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Flash Write Procedure Flash bytes are programmed by software with the following sequence: 1. Disable interrupts (recommended). 2. Erase the 512-byte Flash page containing the target location, as described in Section 14.1.2. 3. Set the PSWE bit (register PSCTL). ...
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C8051F55x/56x/57x 14.2. Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the ...
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The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing ...
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C8051F55x/56x/57x 14.4. Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified ...
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Flash. 14.4.3. System Clock 1. If operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to ...
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C8051F55x/56x/57x SFR Definition 14.2. FLKEY: Flash Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Address = 0xB7; SFR Page = All Pages Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a ...
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SFR Definition 14.3. FLSCL: Flash Scale Bit 7 6 Name Reserved Reserved Reserved Type R/W R/W Reset 0 0 SFR Address = 0xB6; SFR Page = All Pages Bit Name 7:5 Reserved Must Write 000b. 4 FLRT Flash Read Time ...
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C8051F55x/56x/57x SFR Definition 14.4. CCH0CN: Cache Control Bit 7 6 Name Reserved Reserved CHPFEN Type R/W R/W Reset 0 0 SFR Address = 0xE3; SFR Page = 0x0F Bit Name 7:6 Reserved Must Write 00b 5 CHPFEN Cache Prefect Enable ...
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Power Management Modes The C8051F55x/56x/57x devices have three software programmable power management modes: Idle, Stop, and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode is an enhanced power-saving mode implemented by ...
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C8051F55x/56x/57x 15.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital ...
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SFR Definition 15.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87; SFR Page = All Pages Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software ...
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C8051F55x/56x/57x 16. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to ...
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Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the V ...
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C8051F55x/56x/57x Important Note: If the V monitor is being turned on from a disabled state, it should be enabled before selected as a reset source. Selecting the V lized may cause a system reset. In some applications, ...
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SFR Definition 16.1. VDM0CN: V Bit 7 6 VDMEN VDDSTAT VDMLVL Name R/W R Type Varies Varies Reset SFR Address = 0xFF; SFR Page = 0x00 Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V tem ...
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C8051F55x/56x/57x 16.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on ...
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SFR Definition 16.2. RSTSRC: Reset Source Bit 7 6 Name FERROR C0RSEF Type R R Reset 0 Varies Varies SFR Address = 0xEF; SFR Page = 0x00 Bit Name Description 7 Unused Unused. 6 FERROR Flash Error Reset Flag. 5 ...
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C8051F55x/56x/57x 17. External Data Memory Interface and On-Chip XRAM For C8051F55x/56x/57x devices RAM are included on-chip and mapped into the external data memory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on the C8051F568- 9 ...
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Configuring the External Memory Interface Configuring the External Memory Interface consists of four steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins in ...
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C8051F55x/56x/57x Table 17.1. EMIF Pinout (C8051F568-9 and ‘F570-5) 144 Multiplexed Mode Signal Name Port Pin RD P1.6 WR P1.7 ALE P1.5 D0/A0 P3.0 D1/A1 P3.1 D2/A2 P3.2 D3/A3 P3.3 D4/A4 P3.4 D5/A5 P3.5 D6/A6 P3.6 D7/A7 P3.7 A8 P2.0 A9 ...
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SFR Definition 17.1. EMI0CN: External Memory Interface Control Bit 7 6 Name Type Reset 0 0 SFR Address = 0xAA; SFR Page = 0x00 Bit Name 7:0 PGSEL[7:0] XRAM Page Select Bits. The XRAM Page Select Bits provide the high ...
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C8051F55x/56x/57x SFR Definition 17.2. EMI0CF: External Memory Configuration Bit 7 6 Name Type Reset 0 0 SFR Address = 0xB2; SFR Page = 0x0F Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4 Reserved Read = 0b; ...
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Multiplexed Mode The External Memory Interface operates only in a Multiplexed mode. In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this mode, an external latch (74HC373 ...
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C8051F55x/56x/57x 17.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 17.2, based on the EMIF Mode bits in the EMI0CF register (SFR Definition 17.2). These modes are summarized below. ...
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Split Mode with Bank Select When EMI0CF[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and off- chip space. Effective addresses below the internal XRAM size boundary will access on-chip XRAM ...
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C8051F55x/56x/57x SFR Definition 17.3. EMI0TC: External Memory Timing Control Bit 7 6 EAS[1:0] Name R/W Type 1 1 Reset SFR Address = 0xAA; SFR Page = 0x0F Bit Name 7:6 EAS[1:0] EMIF Address Setup Time Bits. 00: Address setup time ...
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Multiplexed Mode 17.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE WR RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE RD WR Figure 17.3. Multiplexed 16-bit ...
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C8051F55x/56x/57x 17.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE WR RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE RD WR Figure 17.4. Multiplexed 8-bit ...
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MOVX with Bank Select: EMI0CF[4:2] = 010 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE WR RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE RD WR Figure ...
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C8051F55x/56x/57x Table 17.2. AC Parameters for External Memory Interface Parameter Description Address/Control Setup Time T ACS Address/Control Pulse Width T ACW Address/Control Hold Time T ACH Address Latch Enable High Time T ALEH Address Latch Enable Low Time T ALEL ...
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Oscillators and Clock Selection C8051F55x/56x/57x devices include a programmable internal high-frequency oscillator, an external oscil- lator drive circuit, and a clock multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN, OSCICRS, and OSCIFIN registers, as shown ...
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C8051F55x/56x/57x SFR Definition 18.1. CLKSEL: Clock Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x8F; SFR Page = 0x0F Bit Name 7:2 Unused Read = 000000b; Write = Don’t Care 1:0 CLKSL[1:0] System Clock ...
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Programmable Internal Oscillator All C8051F55x/56x/57x devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICRS and OSCIFIN registers defined in SFR Definition ...
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C8051F55x/56x/57x SFR Definition 18.2. OSCICN: Internal Oscillator Control Bit 7 6 IOSCEN[1:0] SUSPEND Name R/W R/W Type 1 1 Reset SFR Address = 0xA1; SFR Page = 0x0F Bit Name 7:6 IOSCEN[1:0] Internal Oscillator Enable Bits. 00: Oscillator Disabled. 01: ...
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SFR Definition 18.3. OSCICRS: Internal Oscillator Coarse Calibration Bit 7 6 Name R Type 0 Varies Varies Reset SFR Address = 0xA2; SFR Page = 0x0F Bit Name 7 Unused Read = 0; Write = Don’t Care 6:0 OSCICRS[6:0] Internal ...
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C8051F55x/56x/57x 18.3. Clock Multiplier The Clock Multiplier generates an output clock which is 4 times the input clock frequency scaled by a pro- grammable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7. The Clock Multiplier’s ...
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SFR Definition 18.5. CLKMUL: Clock Multiplier Bit 7 6 MULEN MULINIT MULRDY Name R/W R/W Type 0 0 Reset SFR Address = 0x97; SFR Page = 0x0F Bit Name 7 MULEN Clock Multiplier Enable. 0: Clock Multiplier disabled. 1: Clock ...
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C8051F55x/56x/57x 18.4. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator ...
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SFR Definition 18.6. OSCXCN: External Oscillator Control Bit 7 6 XTLVLD XOSCMD[2:0] Name R Type 0 0 Reset SFR Address = 0x9F; SFR Page = 0x0F Bit Name 7 XTLVLD Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) ...
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C8051F55x/56x/57x 18.4.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 18.1, Option 1. The External Oscillator Frequency Control value (XFCN) ...
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Capacitor values depend on crystal specifications Figure 18.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 18.4.2. External RC Example network is used as an external oscillator source for the MCU, the circuit ...
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C8051F55x/56x/57x Equation 18.2. C Mode Oscillator Frequency For example: Assume V = 2.1 V and kHz VDD) 0.075 MHz = 2.1) Since the frequency of ...
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Port Input/Output Digital and analog resources are available through 33 (C8051F568-9 and ‘F570-5), 25 (C8051F550- (C8051F550-7) I/O pins. Port pins P0.0-P4.0 on the C8051F568-9 and ‘F570-5, port pins P0.0-P3.0 on theC8051F560-7, and port pins P0.0-P2.1 on the ...
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C8051F55x/56x/57x 19.1. Port I/O Modes of Operation Port pins P0.0–P4.0 use the Port I/O cell shown in Figure 19.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, ...
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Interfacing Port I Multi-Voltage System All Port I/O are capable of interfacing to digital logic operating at a supply voltage higher than VDD and less than 5.25 V. Connect the VIO pin to the voltage source of ...
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C8051F55x/56x/57x Table 19.2. Port I/O Assignment for Digital Functions Digital Function Any pin used for GPIO *Note: P3.1–P3.7 are available on the 40-pin packages. P2.2-P3.0 are available 40-pin and 32-pin packages. 19.2.3. Assigning Port I/O Pins to External Digital Event ...
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cia ctio I ...
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C8051F55x/56x/57x ...
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The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD- OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources ...
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C8051F55x/56x/57x SFR Definition 19.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 CP1AE CP1E Name R/W R/W Type 0 0 Reset SFR Address = 0xE1; SFR Page = 0x0F Bit Name 7 CP1AE Comparator1 Asynchronous Output Enable. 0: Asynchronous ...
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SFR Definition 19.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 T1E T0E Name R/W R/W Type 0 0 Reset SFR Address = 0xE2; SFR Page = 0x0F Bit Name 7 T1E T1 Enable unavailable at Port ...
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C8051F55x/56x/57x SFR Definition 19.3. XBR2: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE R/W R/W Type 0 0 Reset SFR Address = 0xC7; SFR Page = 0x0F Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: ...
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Port Match Port match functionality allows system events to be triggered by a logic value change on P0, P1 P3. A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of ...
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C8051F55x/56x/57x SFR Definition 19.6. P1MASK: Port 1 Mask Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF4; SFR Page = 0x00 Bit Name 7:0 P1MASK[7:0] Port 1 Mask Value. Selects P1 pins to be compared to ...
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SFR Definition 19.8. P2MASK: Port 2 Mask Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xB2; SFR Page = 0x00 Bit Name 7:0 P2MASK[7:0] Port 2 Mask Value. Selects P2 pins to be compared to the ...
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C8051F55x/56x/57x SFR Definition 19.10. P3MASK: Port 3 Mask Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xAF; SFR Page = 0x00 Bit Name 7:0 P3MASK[7:0] Port 1 Mask Value. Selects P3 pins to be compared to ...
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Special Function Registers for Accessing and Configuring Port I/O All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable, except for P4 which is only byte addressable. When writing to ...
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C8051F55x/56x/57x SFR Definition 19.13. P0MDIN: Port 0 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF1; SFR Page = 0x0F Bit Name 7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog ...
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SFR Definition 19.15. P0SKIP: Port 0 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD4; SFR Page = 0x0F Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to ...
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C8051F55x/56x/57x SFR Definition 19.17. P1MDIN: Port 1 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF2; SFR Page = 0x0F Bit Name 7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog ...
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SFR Definition 19.19. P1SKIP: Port 1 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD5; SFR Page = 0x0F Bit Name 7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to ...
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C8051F55x/56x/57x SFR Definition 19.21. P2MDIN: Port 2 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF3; SFR Page = 0x0F Bit Name 7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively). Port pins configured for analog ...
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SFR Definition 19.23. P2SKIP: Port 2 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD6; SFR Page = 0x0F Bit Name 7:0 P2SKIP[7:0] Port 2 Crossbar Skip Enable Bits. These bits select Port 2 pins to ...
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C8051F55x/56x/57x SFR Definition 19.25. P3MDIN: Port 3 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF4; SFR Page = 0x0F Bit Name 7:0 P3MDIN[7:0] Analog Configuration Bits for P3.7–P3.0 (respectively). Port pins configured for analog ...
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SFR Definition 19.27. P3SKIP: Port 3Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD7; SFR Page = 0x0F Bit Name 7:0 P3SKIP[7:0] Port 3 Crossbar Skip Enable Bits. These bits select Port 3 pins to be ...
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C8051F55x/56x/57x SFR Definition 19.29. P4MDOUT: Port 4 Output Mode Bit 7 6 Name Type 0 0 Reset SFR Address = 0xAF; SFR Page = 0x0F Bit Name 7:0 P4MDOUT[7:0] Output Configuration Bits for P4.7–P4.0 (respectively). 0: Corresponding P4.n Output is ...
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Local Interconnect Network (LIN0) Important Note: This chapter assumes an understanding of the Local Interconnect Network (LIN) proto- col. For more information about the LIN protocol, including specifications, please refer to the LIN consor- tium (http://www.lin-subbus.org). LIN is an ...
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C8051F55x/56x/57x 20.1. Software Interface with the LIN Controller The selection of the mode (Master or Slave) and the automatic baud rate feature are done though the LIN0 Control Mode (LIN0CF) register. The other LIN registers are accessed indirectly through the ...
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In all of these equations, the results must be rounded down to the nearest integer. The following example shows the steps for calculating the baud rate values for a Master ...
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C8051F55x/56x/57x Table 20.2. Manual Baud Rate Parameters Examples 20 K SYSCLK (MHz 312 0 24 306 300 0 22.1184 0 1 276 200 0 12. ...
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Table 20.3. Autobaud Parameters Examples System Clock (MHz) 22.1184 11.0592 20.3. LIN Master Mode Operation The master node is responsible for the scheduling of messages and sends the header of each frame con- taining the SYNCH BREAK FIELD, SYNCH FIELD, ...
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C8051F55x/56x/57x The application should perform the following steps when an interrupt is requested. 1. Check the DONE bit (LIN0ST.0) and the ERROR bit (LIN0ST.2 performing a master receive operation and the transfer was successful, read the received data ...
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The LIN controller does not directly support LIN Version 1.3 Extended Frames. If the application detects an unknown identifier (e.g. extended identifier), it has to write the STOP bit (LIN0CTRL.7) instead of setting the DTACK (LIN0CTRL.4) ...
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C8051F55x/56x/57x 20.7. LIN Registers The following Special Function Registers (SFRs) and indirect registers are available for the LIN controller. 20.7.1. LIN Direct Access SFR Registers Definitions SFR Definition 20.1. LIN0ADR: LIN0 Indirect Address Register Bit 7 6 Name Type 0 ...
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SFR Definition 20.3. LIN0CF: LIN0 Control Mode Register Bit LINEN MODE ABAUD Name R/W R/W R/W Type Reset SFR Address = 0xC9; SFR Page = 0x0F Bit Name 7 LINEN LIN Interface Enable Bit. ...
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C8051F55x/56x/57x 20.7.2. LIN Indirect Access SFR Registers Definitions Table 20.4 lists the 15 indirect registers used to configured and communicate with the LIN controller. Table 20.4. LIN Registers* (Indirectly Addressable) Name Address Bit7 LIN0DT1 0x00 LIN0DT2 0x01 LIN0DT3 0x02 LIN0DT4 ...