C8051F369-GM Silicon Laboratories Inc, C8051F369-GM Datasheet - Page 246
C8051F369-GM
Manufacturer Part Number
C8051F369-GM
Description
IC 8051 MCU 16K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F369-GM
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
On-chip Adc
21-ch x 10-bit
On-chip Dac
1-ch x 10-bit
A/d Bit Size
10 bit
A/d Channels Available
21
Height
0.83 mm
Length
5 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1651
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F369-GM
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F360/1/2/3/4/5/6/7/8/9
246
Master Mode Timing* (See Figure 20.8 and Figure 20.9)
T
T
T
T
Slave Mode Timing* (See Figure 20.10 and Figure 20.11)
T
T
T
T
T
T
T
T
T
T
*Note: T
MCKH
MCKL
MIS
MIH
SE
SD
SEZ
SDZ
CKH
CKL
SIS
SIH
SOH
SLH
Parameter
SYSCLK
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
is equal to one period of the device system clock (SYSCLK).
Table 20.1. SPI Slave Timing Parameters
Description
Rev. 1.0
1 x T
1 x T
1 x T
2 x T
2 x T
5 x T
5 x T
2 x T
2 x T
6 x T
SYSCLK
Min
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
—
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
SYSCLK
0
+ 20
4 x T
4 x T
4 x T
8 x T
Max
—
—
—
—
—
—
—
—
—
—
SYSCLK
SYSCLK
SYSCLK
SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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