C8051F511-IM Silicon Laboratories Inc, C8051F511-IM Datasheet - Page 258
C8051F511-IM
Manufacturer Part Number
C8051F511-IM
Description
IC 8051 MCU 32K FLASH 40-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F51xr
Specifications of C8051F511-IM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
40-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
33
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4352 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1585 - PLATFORM PROG TOOLSTICK F588
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1563-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F511-IM
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F50x/F51x
25.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
258
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MISO
NSS (4-Wire Mode)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MISO
NSS (4-Wire Mode)
Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0)
Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1)
MSB
MSB
MSB
MSB
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
Rev. 1.2
Bit 4
Bit 4
Bit 4
Bit 4
Bit 3
Bit 3
Bit 3
Bit 3
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
Bit 0
Bit 0
Bit 0
Bit 0
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