C8051F707-GM Silicon Laboratories Inc, C8051F707-GM Datasheet - Page 164
![IC 8051 MCU 16K FLASH 48-QFN](/photos/12/27/122718/c8051f707-gm_sml.jpg)
C8051F707-GM
Manufacturer Part Number
C8051F707-GM
Description
IC 8051 MCU 16K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Specifications of C8051F707-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1606-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F707-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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- Download datasheet (2Mb)
C8051F70x/71x
25.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
cause the device to be released from reset before V
1 ms, the power-on reset delay (T
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
164
RST
Logic HIGH
Logic LOW
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
ramp time is defined as how fast V
DD
RST
monitor reset timing. The maximum V
Figure 25.2. Power-On and V
V
RST
Power-On
PORDelay
Reset
T
) is typically less than 10 ms.
PORDelay
Rev. 1.0
DD
DD
DD
reaches the V
ramps from 0 V to V
DD
Monitor Reset Timing
ramp time is 1 ms; slower ramp times may
Monitor
Reset
RST
VDD
DD
level. For ramp times less than
monitor is enabled following a
RST
). Figure 25.2. plots the
DD
V
settles above
DD
DD
ramp time
t
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