C8051F341-GQ Silicon Laboratories Inc, C8051F341-GQ Datasheet - Page 162
![IC 8051 MCU FLASH 32K 48TQFP](/photos/12/27/122781/c8051f341-gq_sml.jpg)
C8051F341-GQ
Manufacturer Part Number
C8051F341-GQ
Description
IC 8051 MCU FLASH 32K 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheets
1.C8051F349-GQ.pdf
(276 pages)
2.C8051F341-GQ.pdf
(1 pages)
3.C8051F347-GQ.pdf
(296 pages)
Specifications of C8051F341-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 20x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
17-ch x 10-bit
No. Of I/o's
40
Ram Memory Size
2304Byte
Cpu Speed
48MHz
No. Of Timers
4
Rohs Compliant
Yes
Package
48TQFP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
17
Height
1 mm
Length
7 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1452 - ADAPTER PROGRAM TOOLSTICK F340
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1299
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F341-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F341-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F340/1/2/3/4/5/6/7/8/9
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pull-up, digital driver, and digital receiver are disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this
practice is not recommended. To configure a Port pin for digital input, write ‘0’ to the corresponding bit in
register PnMDOUT, and write ‘1’ to the corresponding Port latch (register Pn).
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates
a digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR1 is ‘0’, a weak pull-up is enabled for all Port I/O con-
figured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pull-up is
turned off on an output that is driving a ‘0’ to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the
Port I/O pin-assignments based on the XBRn Register settings.
Important Note: The Crossbar must be enabled to use Ports P0, P1, P2, and P3 as standard Port I/O in
output mode. These Port output drivers are disabled while the Crossbar is disabled. Port 4 always func-
tions as standard GPIO.
162
Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode
Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output
Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
Step 4. Assign Port pins to desired peripherals (XBR0, XBR1).
Step 5. Enable the Crossbar (XBARE = ‘1’).
register (PnMDIN).
Mode register (PnMDOUT).
Rev. 1.1