PIC12F615-E/SN Microchip Technology, PIC12F615-E/SN Datasheet - Page 12

• Manufacturer Part Number: PIC12F615-E/SN
• Description: IC PIC MCU FLASH 1KX14 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F615-E/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS-232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC162083 - HEADER MPLAB ICD2 PIC16F616 8/14
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F609/615/12HV609/615
FIGURE 2-2:
DS41302A-page 10
Note 1:
Unimplemented data memory locations, read as ‘0’.
Indirect Addr.
CMCON0
CMCON1
Registers
STATUS
PCLATH
INTCON
64 Bytes
VRCON
Purpose
TMR1H
T1CON
General
TMR1L
Bank 0
TMR0
GPIO
PIR1
PCL
FSR
Not a physical register.
(1)
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
3Fh
40h
7Fh
File
DATA MEMORY MAP OF
THE PIC12F609/HV609
Accesses 70h-7Fh
Indirect Addr.
OPTION_REG
OSCTUNE
PCLATH
INTCON
STATUS
TRISIO
ANSEL
PCON
Bank 1
WPU
PIE1
PCL
FSR
IOC
(1)
Address
File
EFh
F0h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh
Preliminary
FIGURE 2-3:
Note 1:
Unimplemented data memory locations, read as ‘0’.
Indirect Addr.
PWM1CON
CCP1CON
CMCON0
CMCON1
ADRESH
ADCON0
Registers
CCPR1L
CCPR1H
ECCPAS
STATUS
PCLATH
INTCON
64 Bytes
VRCON
Purpose
TMR1H
General
TMR1L
T1CON
T2CON
Bank 0
TMR2
TMR0
GPIO
PIR1
PCL
FSR
Not a physical register.
(1)
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
3Fh
40h
7Fh
File
DATA MEMORY MAP OF
THE PIC12F615/HV615
© 2006 Microchip Technology Inc.
Accesses 70h-7Fh
Indirect Addr.
OPTION_REG
OSCTUNE
APFCON
ADRESL
STATUS
PCLATH
INTCON
TRISIO
ANSEL
PCON
Bank 1
WPU
PIE1
PCL
FSR
PR2
IOC
(1)
Address
File
EFh
F0h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh