PIC12F615-E/MF Microchip Technology, PIC12F615-E/MF Datasheet - Page 73
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PIC12F615-E/MF
Manufacturer Part Number
PIC12F615-E/MF
Description
IC PIC MCU FLASH 1KX14 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(26 pages)
3.PIC12F609T-ISN.pdf
(8 pages)
4.PIC12F615-EMF.pdf
(196 pages)
Specifications of PIC12F615-E/MF
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
8-DFN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
5
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC12F609T-ISN PDF datasheet
- PIC12F609T-ISN PDF datasheet #2
- PIC12F609T-ISN PDF datasheet #3
- PIC12F615-EMF PDF datasheet #4
- Current page: 73 of 212
- Download datasheet (2Mb)
9.8
This feature can be used to time the duration or interval
of analog events. Clearing the T1GSS bit of the
CMCON1 register will enable Timer1 to increment
based on the output of the comparator. This requires
that Timer1 is on and gating is enabled. See
Section 7.0 “Timer1 Module with Gate Control” for
details.
It is recommended to synchronize the comparator with
Timer1 by setting the CMSYNC bit when the
comparator is used as the Timer1 gate source. This
ensures Timer1 does not miss an increment if the
comparator changes during an increment.
REGISTER 9-2:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
2:
Comparator Gating Timer1
Refer to Section 7.6 “Timer1 Gate”.
Refer to Figure 9-2.
Unimplemented: Read as ‘0’
T1ACS: Timer1 Alternate Clock Select bit
1 = Timer 1 Clock Source is System Clock (F
0 = Timer 1 Clock Source is Instruction Clock (F
CMHYS: Comparator Hysteresis Select bit
1 = Comparator Hysteresis enabled
0 = Comparator Hysteresis disabled
Unimplemented: Read as ‘0’
T1GSS: Timer1 Gate Source Select bit
1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input)
0 = Timer 1 Gate Source is comparator output
CMSYNC: Comparator Output Synchronization bit
1 = Output is synchronized with falling edge of Timer1 clock
0 = Output is asynchronous
U-0
—
CMCON1: COMPARATOR CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
PIC12F609/615/617/12HV609/615
U-0
—
T1ACS
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OSC
CMHYS
R/W-0
9.9
The comparator output can be synchronized with
Timer1 by setting the CMSYNC bit of the CMCON1
register. When enabled, the comparator output is
latched on the falling edge of the Timer1 clock source.
If a prescaler is used with Timer1, the comparator
output is latched after the prescaling function. To
prevent a race condition, the comparator output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. See the Comparator Block Diagram (Figure 9-
2) and the Timer1 Block Diagram (Figure 7-1) for more
information.
OSC
)
(2)
\4)
Synchronizing Comparator Output
to Timer1
U-0
—
x = Bit is unknown
T1GSS
R/W-1
DS41302D-page 73
CMSYNC
R/W-0
bit 0
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