ATTINY5-TS8R Atmel, ATTINY5-TS8R Datasheet - Page 40
ATTINY5-TS8R
Manufacturer Part Number
ATTINY5-TS8R
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY9-MAHR.pdf
(169 pages)
Specifications of ATTINY5-TS8R
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Processor Series
ATTINY5x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY5-TS8R
Manufacturer:
Atmel
Quantity:
8 105
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9.3.4
9.3.5
9.3.6
40
ATtiny4/5/9/10
PCICR – Pin Change Interrupt Control Register
PCIFR – Pin Change Interrupt Flag Register
PCMSK – Pin Change Mask Register
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT3..0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-
rupt Vector. PCINT3..0 pins are enabled individually by the PCMSK Register.
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT3..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:0 – PCINT3..0: Pin Change Enable Mask 3..0
Each PCINT3..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT3..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT3..0 is cleared, pin change interrupt on the corresponding I/O pin
is disabled.
Bit
0x12
Read/Write
Initial Value
Bit
0x11
Read/Write
Initial Value
Bit
0x10
Read/Write
Initial Value
R
R
R
7
–
0
7
–
0
7
–
0
R
R
R
6
–
0
6
–
0
6
–
0
R
R
R
5
–
0
5
–
0
5
–
0
R
R
R
4
–
0
4
–
0
4
–
0
PCINT3
R/W
R
R
3
0
3
–
0
3
–
0
PCINT2
R/W
R
R
2
0
2
–
0
2
–
0
PCINT1
R/W
R
R
1
0
1
–
0
1
–
0
PCINT0
PCIE0
PCIF0
R/W
R/W
R/W
0
0
0
0
0
0
8127D–AVR–02/10
PCMSK
PCICR
PCIFR
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