ATTINY20-SSU Atmel, ATTINY20-SSU Datasheet - Page 43
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATTINY20-SSU
Manufacturer Part Number
ATTINY20-SSU
Description
MCU AVR 2KB FLASH 12MHZ 14SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-SSU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, TWI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY20-SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 43 of 224
- Download datasheet (6Mb)
9.3.4
9.3.5
8235B–AVR–04/11
PCMSK1 – Pin Change Mask Register 1
PCMSK0 – Pin Change Mask Register 0
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 3:0 – PCINT[11:8] : Pin Change Enable Mask 11:8
Each PCINT[11:8] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[11:8] is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[11:8] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bits 7:0 – PCINT[7:0] : Pin Change Enable Mask 7:0
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[7:0] is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
0x0A
Read/Write
Initial Value
Bit
0x09
Read/Write
Initial Value
PCINT7
R/W
R
7
–
0
7
0
PCINT6
R
R/W
6
–
0
6
0
PCINT5
R
5
–
0
R/W
5
0
PCINT4
R
4
–
0
R/W
4
0
PCINT11
R/W
PCINT3
3
0
R/W
3
0
PCINT10
PCINT2
R/W
R/W
2
0
2
0
PCINT9
PCINT1
R/W
R/W
1
0
1
0
PCINT0
PCINT8
ATtiny20
R/W
R/W
0
0
0
0
PCMSK0
PCMSK1
43
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