ATTINY20-MMH Atmel, ATTINY20-MMH Datasheet - Page 140
![MCU AVR 2KB FLASH 12MHZ 20QFN](/photos/30/99/309958/qfn-16_sml.jpg)
ATTINY20-MMH
Manufacturer Part Number
ATTINY20-MMH
Description
MCU AVR 2KB FLASH 12MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, TWI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY20-MMHR
Manufacturer:
ATMEL
Quantity:
20 000
- Current page: 140 of 224
- Download datasheet (6Mb)
17.3.1
17.3.2
17.3.3
140
ATtiny20
Electrical Characteristics
START and STOP Conditions
Bit Transfer
The master provides the clock signal for the transaction, but a device connected to the bus is
allowed to stretch the low level period of the clock to decrease the clock speed.
The TWI follows the electrical specifications and timing of I
with SMBus” on page
Two unique bus conditions are used for marking the beginning (START) and end (STOP) of a
transaction. The master issues a START condition(S) by indicating a high to low transition on the
SDA line while the SCL line is kept high. The master completes the transaction by issuing a
STOP condition (P), indicated by a low to high transition on the SDA line while SCL line is kept
high.
Figure 17-3. START and STOP Conditions
Multiple START conditions can be issued during a single transaction. A START condition not
directly following a STOP condition, are named a Repeated START condition (Sr).
As illustrated by
period of the SCL line. Consequently the SDA value can only be changed during the low period
of the clock. This is ensured in hardware by the TWI module.
Figure 17-4. Data Validity
Combining bit transfers results in the formation of address and data packets. These packets
consist of 8 data bits (one byte) with the most significant bit transferred first, plus a single bit not-
acknowledge (NACK) or acknowledge (ACK) response. The addressed device signals ACK by
pulling the SCL line low, and NACK by leaving the line SCL high during the ninth clock cycle.
Figure 17-4
144.
a bit transferred on the SDA line must be stable for the entire high
2
C and SMBus. See
“Compatibility
8235B–AVR–04/11
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