ATTINY24A-MUR Atmel, ATTINY24A-MUR Datasheet - Page 38
ATTINY24A-MUR
Manufacturer Part Number
ATTINY24A-MUR
Description
MCU AVR 2KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY24A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8. System Control and Reset
8.1
38
Resetting the AVR
ATtiny24A/44A/84A
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in
reset circuitry are given in
Figure 8-1.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in
BODLEVEL[2:0]
RSTDISBL
Reset Logic
Pull-up Resistor
FILTER
SPIKE
Table 20-4 on page
Figure 8-1
CKSEL[3:0]
Power-on Reset
Reset Circuit
SUT[1:0]
Brown-out
Watchdog
Oscillator
Generator
Circuit
Clock
shows the reset logic. Electrical parameters of the
176.
CK
Register (MCUSR)
MCU Status
DATA BUS
“Clock Sources” on page
Delay Counters
TIMEOUT
25.
8183C–AVR–03/11
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