PIC16F688-I/STG Microchip Technology, PIC16F688-I/STG Datasheet - Page 115

• Manufacturer Part Number: PIC16F688-I/STG
• Description: IC PIC MCU FLASH 4KX14 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/STG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• For Use With: XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2
1997 Microchip Technology Inc.
Control Register
bit 7:5
bit 4
bit 3
bit 2
bit 1
bit 0
Register 7-1: EECON1 Register
bit 7
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
1 = initiates a write cycle. The bit is cleared by hardware once write is complete.
0 = Write cycle to the data EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read. Read takes one cycle. RD is cleared in hardware.
0 = Does not initiate an EEPROM read
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
Note 1: Future devices will have this bit in the PIR register.
U-0
The WR bit can only be set (not cleared) in software.
The RD bit can only be set (not cleared) in software.
(any MCLR reset or any WDT reset during normal operation)
—
U-0
—
W = Writable bit
U-0
Section 7. Data EEPROM
—
EEIF
R/W-1
(1)
S = Settable bit
- n = Value at POR reset
WRERR
R/W-1
WREN
R/W-x
R/S-0
WR
DS31007A-page 7-3
bit 0
R/S-x
RD
7