PIC16F688-E/P Microchip Technology, PIC16F688-E/P Datasheet - Page 34

• Manufacturer Part Number: PIC16F688-E/P
• Description: IC MCU PIC FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTER
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
REGISTER 4-2:
REGISTER 4-3:
DS41203B-page 32
bit 7-6:
bit 5-0:
bit 7-6
bit 5-4
bit 3
bit 2-0
TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h OR 185h)
WPUA – WEAK PULL-UP REGISTER (ADDRESS: 95h)
bit 7
bit 7
Unimplemented: Read as ‘0’
TRISA<5:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Unimplemented: Read as ‘0’
WPUA<5:4>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
WPUA<2:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Legend:
R = Readable bit
- n = Value at POR
Legend:
R = Readable bit
- n = Value at POR
Note 1: TRISA<3> always reads ‘1’.
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
U-0
U-0
—
—
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
2: The weak pull-up device is automatically disabled if the pin is in output mode
3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
(TRISA = 0).
the Configuration Word.
U-0
U-0
—
—
TRISA5
WPUA5
R/W-1
R/W-1
Preliminary
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
TRISA4
WPUA4
R/W-1
R/W-1
TRISA3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
R-1
WPUA2
R/W-1
TRISA2
R/W-1
 2004 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
WPUA1
R/W-1
TRISA1
R/W-1
WPUA0
TRISA0
R/W-1
R/W-1
bit 0
bit 0