PIC16F688-E/ML Microchip Technology, PIC16F688-E/ML Datasheet - Page 34
![IC PIC MCU FLASH 4KX14 16QFN](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F688-E/ML
Manufacturer Part Number
PIC16F688-E/ML
Description
IC PIC MCU FLASH 4KX14 16QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
Specifications of PIC16F688-E/ML
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-QFN
Controller Family/series
PIC16F
No. Of I/o's
12
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
2
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, RS- 232, SCI, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- Current page: 34 of 204
- Download datasheet (4Mb)
PIC16F688
FIGURE 3-9:
TABLE 3-2:
DS41203E-page 32
CONFIG
INTCON
OSCCON
OSCTUNE
PIE1
PIR1
Legend:
Note 1:
Clock Monitor Output
Name
2:
Sample Clock
(2)
Note:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (CONFIG) for operation of all register bits.
OSCFIF
System
Output
Clock
EEIE
EEIF
Bit 7
CPD
GIE
—
—
(Q)
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
FSCM TIMING DIAGRAM
IRCF2
PEIE
ADIE
ADIF
Bit 6
CP
—
MCLRE
IRCF1
RCIE
RCIF
Bit 5
T0IE
—
Test
PWRTE
IRCF0
TUN4
Bit 4
INTE
C2IE
C2IF
WDTE
OSTS
TUN3
RAIE
Bit 3
C1IE
C1IF
FOSC2
OSFIE
OSFIF
TUN2
Bit 2
T0IF
HTS
Test
Oscillator
Failure
FOSC1
TUN1
Bit 1
INTF
TXIE
TXIF
LTS
TMR1IE
TMR1IF
FOSC0
TUN0
RAIF
Bit 0
SCS
© 2009 Microchip Technology Inc.
Detected
0000 000x
-110 x000
---0 0000
0000 0000
0000 0000
POR, BOR
Value on
Failure
—
Test
0000 000x
-110 x000
---u uuuu
0000 0000
0000 0000
Resets
Value on
all other
—
(1)
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