PIC12CE518-04/P Microchip Technology, PIC12CE518-04/P Datasheet - Page 103

• Manufacturer Part Number: PIC12CE518-04/P
• Description: IC MCU OTP 512X12 W/EE 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE518-04/P

• Core Size: 8-Bit
• Program Memory Size: 768B (512 x 12)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 16Byte
• Ram Memory Size: 25Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 25 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

6.3.3
1997 Microchip Technology Inc.
Banking
The data memory is partitioned into four banks. Each bank contains General Purpose Registers
and Special Function Registers. Switching between these banks requires the RP0 and RP1 bits
in the STATUS register to be configured for the desired bank when using direct addressing. The
IRP bit in the STATUS register is used for indirect addressing.
Table 6-1:
Each Bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the
Special Function Registers. Above the Special Function Registers are General Purpose Regis-
ters. All data memory is implemented as static RAM. All Banks may contain special function reg-
isters. Some “high use” special function registers from Bank0 are mirrored in the other banks for
code reduction and quicker access.
Through the evolution of the products, there are a few variations in the layout of the Data Memory.
The data memory organization that will be the standard for all new devices is shown in
Figure
reduce the software overhead for context switching. The registers in bold will be in every device.
The other registers are peripheral dependent. Not every peripheral’s registers are shown,
because some file addresses have a different registers from those shown. As with all the figures,
tables, and specifications presented in this reference guide, verify the details with the device spe-
cific data sheet.
Figure 6-4: Direct Addressing
Accessed
Bank
RP1 RP0
bank select
0
1
2
3
6-5. This Memory map has the last 16-bytes mapped across all memory banks. This is to
Section 6. Memory Organization
Direct and Indirect Addressing of Banks
(RP1:RP0)
Direct
location select
6
Direct Addressing
0 0
0 1
1 0
1 1
Data
Memory
from opcode
Indirect
(IRP)
7Fh
00h
0
1
Bank0
00
0
Bank1
01
Bank2
10
Bank3
11
DS31006A-page 6-9
7Fh
6