PIC16F685-E/P Microchip Technology, PIC16F685-E/P Datasheet - Page 185
![IC PIC MCU FLASH 4KX14 20DIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC16F685-E/P
Manufacturer Part Number
PIC16F685-E/P
Description
IC PIC MCU FLASH 4KX14 20DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
Specifications of PIC16F685-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
For Use With
AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOICDM163029 - BOARD PICDEM FOR MECHATRONICSACICE0203 - MPLABICE 20P 300 MIL ADAPTER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- Current page: 185 of 306
- Download datasheet (6Mb)
13.3
To enable the serial port, SSP Enable bit SSPEN of the
SSPCON register must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRISB and TRISC registers) appropriately
programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<7> bit cleared
• SCK (Master mode) must have TRISB<6> bit
• SCK (Slave mode) must have TRISB<6> bit set
• SS must have TRISC<6> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRISB and TRISC) registers to the opposite
value.
FIGURE 13-2:
© 2008 Microchip Technology Inc.
cleared
Enabling SPI I/O
SPI Master SSPM<3:0> = 00xxb
MSb
Serial Input Buffer
Processor 1
Shift Register
SPI MASTER/SLAVE CONNECTION
(SSPBUF)
(SSPSR)
PIC16F631/677/685/687/689/690
LSb
SDO
SCK
SDI
Serial Clock
13.4
Figure 13-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
SDO
SCK
SDI
Typical Connection
SPI Slave SSPM<3:0> = 010xb
MSb
Serial Input Buffer
Shift Register
(SSPBUF)
(SSPSR)
Processor 2
LSb
DS41262E-page 183
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