PIC16F690-E/P Microchip Technology, PIC16F690-E/P Datasheet - Page 183
PIC16F690-E/P
Manufacturer Part Number
PIC16F690-E/P
Description
IC PIC MCU FLASH 4KX14 20DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
5.PIC16F677-ISO.pdf
(294 pages)
Specifications of PIC16F690-E/P
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
20-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SPI/SSP/EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-1, DM163029
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
PIC16F690DM-PCTLHS - BOARD DEMO PICTAIL HUMIDITY SNSRAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOICDM163029 - BOARD PICDEM FOR MECHATRONICSACICE0203 - MPLABICE 20P 300 MIL ADAPTER
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- PIC16F677-ISO PDF datasheet #5
- Current page: 183 of 306
- Download datasheet (6Mb)
REGISTER 13-2:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1: PIC16F687/PIC16F689/PIC16F690 only.
WCOL
R/W-0
2: When this mode is selected, any reads or writes to the SSPADD SFR address actually accesses the SSPMSK register.
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level (Microwire default)
0 = Idle state for clock is a low level (Microwire alternate)
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I
0111 = I
1000 = Reserved
1001 = Load SSPMSK register at SSPADD SFR address
1010 = Reserved
1011 = I
1100 = Reserved
1101 = Reserved
1110 = I
1111 = I
2
2
2
SSPOV
R/W-0
C™ mode:
C mode:
C mode:
data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only
transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new recep-
tion (and transmission) is initiated by writing to the SSPBUF register.
Transmit mode. SSPOV must be cleared in software in either mode.
SSPCON: SYNC SERIAL PORT CONTROL REGISTER
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Firmware Controlled Master mode (slave IDLE)
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
PIC16F631/677/685/687/689/690
OSC
OSC
OSC
R/W-0
CKP
/4
/16
/64
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
(2)
(2)
SSPM2
R/W-0
(2)
(1)
x = Bit is unknown
SSPM1
R/W-0
(2)
DS41262E-page 181
SSPM0
R/W-0
(2)
bit 0
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