ATMEGA48P-20MMUR Atmel, ATMEGA48P-20MMUR Datasheet - Page 264

• Manufacturer Part Number: ATMEGA48P-20MMUR
• Description: MCU AVR 4K FLASH 20MHZ 28QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA48P-20MMUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.9.5
8025L–AVR–7/10
DIDR0 – Digital Input Disable Register 0
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Table 23-6.
• Bits 7:6 – Reserved
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when DIDR0 is written.
• Bit 5:0 – ADC5D:ADC0D: ADC5:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC5:0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do not
require Digital Input Disable bits.
Bit
(0x7E)
Read/Write
Initial Value
ADTS2
0
0
0
0
1
1
1
1
ADC Auto Trigger Source Selections
R
7
–
0
ADTS1
R
6
–
0
0
0
1
1
0
0
1
1
ADC5D
R/W
5
0
ADC4D
R/W
ADTS0
4
0
0
1
0
1
0
1
0
1
ADC3D
R/W
3
0
ATmega48P/88P/168P
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
ADC2D
R/W
2
0
ADC1D
R/W
1
0
ADC0D
R/W
0
0
.
DIDR0
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