PIC12CE519-04/P Microchip Technology, PIC12CE519-04/P Datasheet - Page 261
PIC12CE519-04/P
Manufacturer Part Number
PIC12CE519-04/P
Description
IC MCU OTP 1KX12 W/EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12C508A-04SM.pdf
(113 pages)
3.PIC12C508A-04SM.pdf
(4 pages)
4.PIC12CE518-04SM.pdf
(16 pages)
Specifications of PIC12CE519-04/P
Program Memory Type
OTP
Program Memory Size
1.5KB (1K x 12)
Package / Case
8-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Eeprom Size
16 x 8
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
41 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
1
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE519-04/P
Manufacturer:
Microchip
Quantity:
710
Part Number:
PIC12CE519-04/P
Manufacturer:
MIC
Quantity:
20 000
- PIC16F688T-ISL PDF datasheet
- PIC12C508A-04SM PDF datasheet #2
- PIC12C508A-04SM PDF datasheet #3
- PIC12CE518-04SM PDF datasheet #4
- Current page: 261 of 688
- Download datasheet (3Mb)
16.3.5
1997 Microchip Technology Inc.
SSPIF
Interrupt flag
SCK
(CKP = 0)
SCK
(CKP = 1)
Slave Operation
SDO
SDI
In slave mode, the data is transmitted and received as the external clock pulses appear on SCK.
When the last bit is latched the SSPIF interrupt flag bit is set.
The clock polarity is selected by appropriately programming the CKP bit (SSPCON<4>). This
then would give waveforms for SPI communication as shown in
where the MSb is transmitted first. When in slave mode the external clock must meet the mini-
mum high and low times.
In sleep mode, the slave can transmit and receive data and wake the device from sleep if the
interrupt is enabled.
Figure 16-4: SPI Mode Waveform (Slave Mode w/o SS Control)
bit7
bit7
bit6
bit5
bit4
bit3
Section 16. BSSP
bit2
bit1
Figure 16-5
DS31016A-page 16-11
bit0
bit0
and
Next Q4 Cycle
Figure 16-5
after Q2
16
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