ATMEGA8A-AUR Atmel, ATMEGA8A-AUR Datasheet - Page 121

• Manufacturer Part Number: ATMEGA8A-AUR
• Description: MCU AVR 8KB FLASH 16MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.11 Register Description
17.11.1
8159D–AVR–02/11
TCCR2 – Timer/Counter Control Register
• Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2 is written when
operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare
Match is forced on the waveform generation unit. The OC2 output is changed according to its
COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the
value present in the COM21:0 bits that determines the effect of the forced compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2 as TOP.
The FOC2 bit is always read as zero.
• Bit 6,3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 17-2.
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set
in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting.
normal or CTC mode (non-PWM).
Bit
Read/Write
Initial Value
Mode
0
1
2
3
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
112.
WGM21
Table 17-3
(CTC2)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
Waveform Generation Mode Bit Description
FOC2
W
7
0
WGM20
(PWM2)
shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
WGM20
R/W
0
1
0
1
6
0
COM21
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
R/W
5
0
COM20
(1)
R/W
4
0
WGM21
R/W
3
0
Table 17-2
0xFF
0xFF
TOP
0xFF
OCR2
CS22
R/W
2
0
TOP
Update of
OCR2
Immediate
Immediate
BOTTOM
CS21
and
R/W
1
0
“Modes of Operation”
ATmega8A
CS20
R/W
0
0
TOV2 Flag
Set
MAX
BOTTOM
MAX
MAX
TCCR2
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