ATMEGA88A-MMH Atmel, ATMEGA88A-MMH Datasheet - Page 286
![IC MCU AVR 8K FLASH 28QFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATMEGA88A-MMH
Manufacturer Part Number
ATMEGA88A-MMH
Description
IC MCU AVR 8K FLASH 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA88A-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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26.8.4
26.8.5
26.8.6
26.8.7
26.8.8
26.8.9
8271C–AVR–08/10
Using the SPM Interrupt
Consideration While Updating BLS
Prevent Reading the RWW Section During Self-Programming
Setting the Boot Loader Lock Bits by SPM
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SELFPRGEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of
polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors
should be moved to the BLS section to avoid that an interrupt is accessing the RWW section
when it is blocked for reading. How to move the interrupts is described in
58.
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW
section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS
as described in
addressing the RWW section after the programming is completed, the user software must clear
the RWWSB by writing the RWWSRE. See
on page 288
To set the Boot Loader Lock bits and general Lock Bits, write the desired data to R0, write
“X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
See
Flash access.
If bits 5...0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM
instruction is executed within four cycles after BLBSET and SELFPRGEN are set in SPMCSR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with 0x0001 (same as used for reading the lO
is also recommended to set bits 7 and 6 in R0 to “1” when writing the Lock bits. When program-
ming the Lock bits the entire Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
R0
Table 26-2
for an example.
and
”Watchdog Timer” on page
7
1
Table 26-3
6
1
for how the different settings of the Boot Loader bits affect the
BLB12
5
BLB11
”Simple Assembly Code Example for a Boot Loader”
4
51, or the interrupts must be disabled. Before
BLB02
3
BLB01
2
ck
bits). For future compatibility it
LB2
1
”Interrupts” on page
LB1
0
286
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