PIC16F1934-E/ML Microchip Technology, PIC16F1934-E/ML Datasheet - Page 289

• Manufacturer Part Number: PIC16F1934-E/ML
• Description: IC PIC MCU FLASH 256KX7 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1934-E/ML

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 44-QFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART/MI2C/SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

22.4
All MSSP I
shifted out MSb first. Six SFR registers and 2 interrupt
flags interface the module with the PIC
troller and user software. Two pins, SDA and SCL, are
exercised by the module to communicate with other
external I
22.4.1
Selection of any I
forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRIS bits.
22.4.2
All communication in I
byte is sent from a Master to a Slave or vice-versa, fol-
lowed by an Acknowledge bit sent back. After the 8th
falling edge of the SCL line, the device outputting data
on the SDA changes that pin to an input and reads in
an acknowledge value on the next clock pulse.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
22.4.3
There is language and terminology in the description
of I
I
used in the rest of this document without explana-
tion.
specification.
© 2008 Microchip Technology Inc.
2
C. That word usage is defined below and may be
Note: Data is tied to output zero when an I
2
C communication that have definitions specific to
This table was adapted from the Phillips I
I
SDA AND SCL PINS
BYTE FORMAT
DEFINITION OF I
2
2
is enabled.
C devices.
C
2
C communication is byte oriented and
MODE
2
C mode with the SSPEN bit set,
2
C is done in 9-bit segments. A
2
C TERMINOLOGY
®
microcon-
2
C mode
Preliminary
2
C
TABLE 22-2:
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Synchronization Procedure to synchronize the
Idle
Active
Addressed
Slave
Matching
Address
Write Request
Read Request
Clock Stretching When a device on the bus hold
Bus Collision
PIC16F193X/LF193X
TERM
I
2
The device which shifts data out
onto the bus.
The device which shifts data in
from the bus.
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
The device addressed by the mas-
ter.
A bus with more than one device
that can initiate data transfers.
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
clocks of two or more devices on
the bus.
No master is controlling the bus,
and both SDA and SCL lines are
high.
Any time one or more master
devices are controlling the bus.
Slave device that has received a
matching address and is actively
being clocked by a master.
Address byte that is clocked into a
slave that matches the value
stored in SSPADD.
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
SCL low to stall communication.
Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.
C BUS TERMS
Description
DS41364A-page 287