PIC16F883-E/SP Microchip Technology, PIC16F883-E/SP Datasheet - Page 181
![IC PIC MCU FLASH 4KX14 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16F883-E/SP
Manufacturer Part Number
PIC16F883-E/SP
Description
IC PIC MCU FLASH 4KX14 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.MCP1631RD-MCC2.pdf
(328 pages)
3.PIC16F882-ISS.pdf
(16 pages)
4.PIC16F882-ISS.pdf
(36 pages)
5.PIC16F883-ISO.pdf
(288 pages)
Specifications of PIC16F883-E/SP
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
MSSP/EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164120-3
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCP1631RD-MCC2 - REFERENCE DESIGN MCP1631HVDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- MCP1631RD-MCC2 PDF datasheet #2
- PIC16F882-ISS PDF datasheet #3
- PIC16F882-ISS PDF datasheet #4
- PIC16F883-ISO PDF datasheet #5
- Current page: 181 of 288
- Download datasheet (5Mb)
13.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four modes
of SPI are supported. To accomplish communication,
typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in any
Slave mode of operation:
• Slave Select (SS) – RA5/SS/AN4
13.3.1
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits SSPCON<5:0> and SSPSTAT<7:6>.
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock polarity (Idle state of SCK)
• Data input sample phase (middle or end of data
• Clock edge (output data on rising/falling edge of
• Clock rate (Master mode only)
• Slave Select mode (Slave mode only)
Figure 13-1 shows the block diagram of the MSSP
module, when in SPI mode.
© 2007 Microchip Technology Inc.
output time)
SCK)
SPI Mode
OPERATION
PIC16F882/883/884/886/887
Preliminary
FIGURE 13-1:
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the buffer full-detect bit BF of the SSP-
STAT register and the interrupt flag bit SSPIF of the
PIR1 register are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL of the SSPCON register
will be set. User software must clear the WCOL bit so
that it can be determined if the following write(s) to the
SSPBUF register completed successfully.
SDO
SCK
SDI
Note: I/O pins have diode protection to V
SS
Read
SS Control
Select
SMP:CKE
Edge
bit 0
Enable
Select
Edge
SSPBUF Reg
MSSP BLOCK DIAGRAM
(SPI MODE)
TRIS bit
Data to TX/RX in SSPSR
SSPSR Reg
2
SSPM<3:0>
Clock Select
4
2
DS41291D-page 179
(
Write
Prescaler
4, 16, 64
TMR2 Output
Clock
Shift
DD
Data Bus
Internal
and V
2
T
OSC
SS
)
.
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