PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 262
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PIC12C672T-10/SM
Manufacturer Part Number
PIC12C672T-10/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672T-10/SM
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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PICmicro MID-RANGE MCU FAMILY
16.3.6
DS31016A-page 16-12
SCK
(CKP = 0)
SCK
(CKP = 1)
SS
SSPIF
SDO
SDI
Slave Select Mode
The SS pin allows a synchronous slave mode. The SPI must be in slave mode
(SSPCON<3:0> = 04h) and the TRIS bit must be set the for the synchronous slave mode to be
enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is
driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a
transmitted byte, and becomes a floating output. If the SS pin is taken low without resetting SPI
mode, the transmission will continue from the point at which it was taken high. To clear the bit
counter the Basic SSP module must be disabled and then re-enabled. External pull-up/pull-down
resistors may be desirable, depending on the application.
To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the
SPI needs to operate as a receiver the SDO pin can be configured as an input. This disables
transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot
create a bus conflict.
Figure 16-5: SPI Mode Waveform (Slave Mode with ss Control)
bit7
bit7
bit6
bit5
bit4
bit3
bit2
Next Q4 Cycle
after Q2
1997 Microchip Technology Inc.
bit1
bit0
bit0
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