PIC16LF648A-I/SS Microchip Technology, PIC16LF648A-I/SS Datasheet - Page 90
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PIC16LF648A-I/SS
Manufacturer Part Number
PIC16LF648A-I/SS
Description
IC PIC MCU FLASH 4KX14 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F627A-IP.pdf
(180 pages)
2.PIC16LF627A-IP.pdf
(8 pages)
3.PIC16LF627A-ISO.pdf
(180 pages)
Specifications of PIC16LF648A-I/SS
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Controller Family/series
PIC16LF
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Data Rom Size
256 B
Height
1.75 mm
Length
7.2 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
5.3 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16LF648A-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F627A/628A/648A
12.5.2
The operation of the Synchronous Master and Slave
modes is identical except in the case of the Sleep
mode. Also, bit SREN is a “don’t care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS40044G-page 90
Legend:
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.
Address
Address
0Ch
8Ch
0Ch
1Ah
8Ch
18h
19h
98h
99h
18h
98h
99h
TXREG USART Transmit Data Register
SPBRG Baud Rate Generator Register
RCREG USART Receive Data Register
SPBRG Baud Rate Generator Register
RCSTA
TXSTA
RCSTA
TXSTA
USART SYNCHRONOUS SLAVE
RECEPTION
Name
Name
PIR1
PIE1
PIR1
PIE1
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission.
SPEN
CSRC
CSRC
SPEN
Bit 7
EEIF
EEIE
EEIF
EEIE
Bit 7
CMIF
CMIE
CMIE
Bit 6
CMIF
RX9
Bit 6
TX9
RX9
TX9
SREN CREN
TXEN SYNC
SREN CREN
TXEN SYNC
RCIF
RCIE
Bit 5
RCIF
RCIE
Bit 5
Bit 4
TXIF
TXIE
Bit 4
TXIF
TXIE
ADEN
ADEN
Bit 3
Bit 3
—
—
—
—
—
—
CCP1IF TMR2IF TMR1IF 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000
CCP1IF TMR2IF TMR1IF 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000
BRGH
FERR
BRGH
FERR
Follow these steps when setting up a Synchronous
Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 2
Bit 2
TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If an OERR error occurred, clear the error by
clearing bit CREN.
OERR
TRMT
OERR
TRMT
Bit 1
Bit 1
RX9D
TX9D
RX9D
TX9D
Bit 0
Bit 0
© 2009 Microchip Technology Inc.
0000 000x
0000 0000
0000 -010
0000 0000
0000 000x
0000 0000
0000 -010
0000 0000
Value on
Value on
POR
POR
other Resets
other Resets
Value on all
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
Value on all
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000