PIC12CE673-04I/P Microchip Technology, PIC12CE673-04I/P Datasheet - Page 116
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12CE673-04I/P
Manufacturer Part Number
PIC12CE673-04I/P
Description
IC MCU OTP 1KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE673-04I/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
16Byte
Ram Memory Size
128Byte
Cpu Speed
4MHz
No.
RoHS Compliant
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE673-04I/P
Manufacturer:
Microchip Technology
Quantity:
135
- PIC16F688T-ISL PDF datasheet
- PIC12CE673-10P PDF datasheet #2
- PIC12CE673-10P PDF datasheet #3
- PIC12CE673-10P PDF datasheet #4
- PIC12CE673-10P PDF datasheet #5
- Current page: 116 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
7.3
7.4
DS31007A-page 7-4
EEADR
EECON1 and EECON2 Registers
The EEADR register can address up to a maximum of 256 bytes of data EEPROM.
The unused address bits are decoded. This means that these bits must always be '0' to ensure
that the address is in the Data EEPROM memory space.
EECON1 is the control register with five low order bits physically implemented. The upper-three
bits are unimplemented and read as '0's.
Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at completion of the read or write operation. The
inability to clear the WR bit in software prevents the accidental, premature termination of a write
operation.
The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted by a MCLR reset or a WDT time-out reset
during normal operation. In these situations, following reset, the user can check the WRERR bit
and rewrite the location. The data and address will be unchanged in the EEDATA and
EEADR registers.
Interrupt flag bit EEIF is set when write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is
used exclusively in the Data EEPROM write sequence.
1997 Microchip Technology Inc.
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